Analog to digital converter circuit

ABSTRACT

An analog/digital converter circuit including a plurality of reference resistance elements dividing a voltage between two reference potentials to provide a plurality of reference voltages; a plurality of switching blocks which are activated by an upper data conversion output signal in units of rows and compare the respective reference voltages with an input signal to be converted to provide a differential output; an upper data encoder which compares the reference voltage supplied to a switching block positioned at a specific position of the switching block matrix with the input signal to provide a plurality of conversion codes of the upper significant bits; a lower data comparator circuit having first and second comparators with weights N.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an analog/digital converter circuit (hereinafter abbreviated as an A/D converter circuit) for converting an analog signal to a digital signal, and more particularly the present invention relates to a serial/parallel type A/D converter circuit for converting an analog signal to a digital signal with two stages that form an upper data part and a lower data part.

2. Description of the Related Art

Various types of analog-to-digital conversion systems have been proposed, in one such system known as a parallel-type (flash-type) A/D converter the circuit quantizes the amplitude of the analog signal and converts the quantized signal to a digital code.

In such a parallel-type A/D converter circuit, high speed operation is possible, however when the number of the conversion bits is n, at least (2^(n) -1) comparators are necessary for implementation of the circuit. A total of 255 comparators are necessary to obtain an 8-bit conversion code, and it is necessary to form several tens of thousands active elements by integration into a circuit in order to obtain a digital code having higher resolution.

For this reason, a parallel-type A/D converter circuit has the advantage that high speed processing is possible, but it is undesirable due to increases in which is required power consumption and the large surface area for the chip.

Therefore, a so-called serial/parallel type A/D converter circuit has been proposed in which, for conversion of the analog signal to n bits of resolution. In this circuit first the analog signal is digitized by rough quantization, so that an "a" bit conversion code including the most significant bit (MSB) is obtained, and in order to reduce the error of this upper data conversion code, that is, the quantization noise, the upper data quantization range is finely divided and digitized, so that the lower data [b (n-a)] bit conversion code including the lower significant bit (LSB) is obtained.

FIG. 1 is a structural view showing an outline of one such serial/parallel type A/D converter circuit which illustrates the circuit configuration for converting an analog signal to a 4-bit digital code.

In FIG. 1, R₁ to R₁₆ denote reference resistance elements serially connected between terminals of reference voltages V_(RT) to V_(RB) (0 to -2 V); C_(u1) to C_(u3) denote upper data comparators which have one input terminal connected to an input line of an input analog signal V_(IN) to be converted and the other input terminal connected to the input line of the reference voltages (V₄, V₈, V₁₂) of the rough quantization level divided by reference resistance elements R₁ to R₁₆ ; B_(u1) to B_(u3) denote buffers for obtaining the complementary outputs of the outputs of upper data comparators C_(u1) to C_(u3) ; A_(u1) to A_(u4) denote AND gates; S_(a1) to S_(a12) denote switching blocks arranged in the form of a matrix comprising four rows and three columns; C_(d1) to C_(d3) denote lower data comparators with one input terminal connected to the input line of the analog signal V_(IN) and the other side input terminal connected to the output terminals of the switching blocks S_(a1) to S_(a12) ; E_(u1) denotes an upper data encoder which encodes the result of differentiation of binary signals output from the upper data comparators C_(u1) to C_(u3) and converts the same to for example a 2-bit binary code (or complementary code of 2); and E_(d1) denotes a lower data encoder which converts the result of differentiation of the binary signals output from the lower data comparators C_(d1) to C_(d3) to a 2-bit binary code; respectively.

The switching blocks S_(a1) to S_(a12) are controlled to turn on or off in accordance with the data "1" and "0" of the output level of the AND gates A_(u1) to A_(u4).

For example, when a signal of the "1" level is output from the AND gate A_(u1), control is performed so that the switching blocks S_(a1) to S_(a3) become an ON state; when the signal of the "1" level is output from the AND gate A_(u2), control is performed so that the switching blocks S_(a4) to S_(a6) become an ON state; when the signal of the "1" level is output from the AND gate A_(u3), control is performed so that the switching blocks S_(a7) to S_(a9) become an ON state; and when the signal of the "1" level is output from the AND gate A_(u4), control is performed so that the switching blocks S_(a10) to S_(a12) become an ON state;

In the serial/parallel type A/D converter circuit having such a structure, as shown in for example FIG. 2, the input analog signal V_(IN) is sampled at the using point of the sampling pulse P_(S), and the sampling voltage V_(S) thereof is supplied to the upper data encoder E_(u1) and the lower data encoder E_(d1).

At the upper data encoder E_(u1), when the sampling voltage V_(S) is supplied, the binary signal outputs of the upper data comparators C_(u1) to C_(u3) are converted to the code signals D₀ and D₁ of the upper significant 2 bits at the point of time T_(H) of trailing edge (point of time lagged by τ_(A)) of the clock signal CLK and output.

At the lower data encoder E_(d1), when the sampling voltage V_(S) is supplied, the binary signal outputs of the lower data comparators C_(d1) to C_(d3) are converted to the code signals D₂ and D₃ of the lower significant 2 bits at the point of time T_(L) of trailing (point of time lagged by τ_(B)) of the clock signal CLK,

Explaining this more concretely, reference voltages V₄, V₈, and V₁₂ of the rough quantization level, divided by the reference resistance elements R₁ to R₁₆ and the input analog signal V_(IN) are compared by the upper data comparators C_(u1) to C_(u3).

As a result of this comparison, for example, when V₄ <V_(IN) <V₈, the output of the upper data comparator C_(u3) becomes the high level at a high potential ("1"), and the outputs of the upper data comparators C_(u2) and C_(u3) become the low level at a low potential ("0").

Thus, at the output of the AND gates A_(u1) to A_(u4), only the output of the AND gate A_(u2) becomes "1", and the outputs of the other AND gates A_(u1), A_(u3), and A_(u4) become "0".

As a result, the code [01] is output as the upper significant 2 bits of the conversion code from the upper data encoder E_(u1).

Next, in a state where the upper significant 2 bits of the conversion code are latched, the signal of the "1" level output from the AND gate A_(u2) is input to the switching blocks S_(a4) to S_(a6). By this, the switching blocks S_(a4) to S_(a6) become an ON state.

Along with the switching blocks S_(a4) to S_(a6) becoming the ON state, the sampled analog signal V_(IN) existing at the level represented as V₄ <V_(IN) <V₈ is further divided by the resistance elements R₄ to R₆, and regulated reference voltages V₅, V₆, and V₇ are input via the switching blocks S_(a4), S_(a5), and S_(a6) to the other input terminals of the lower data comparators C_(d3), C_(d2), and C_(d1), respectively.

In the lower data comparators C_(d3), C_(d2), and C_(d1), the input reference voltages V₅, V₆, and V₇ are compared with the analog signal V_(IN) which is input to the one side input terminals of the same and the result of comparison is output to the lower data encoder E_(d1).

As a result of this comparison, when for example V₆ <V_(IN) <V₇, the lower significant 2 bits of the conversion code [10] are output from the lower data encoder E_(d1).

As a result of the above, a 4-bit conversion code [0110] of the analog signal V_(IN) will be output from the upper data and lower data encoders E_(u1) and E_(u2).

This serial/parallel type A/D converter circuit outputs the conversion code while dividing the same to upper significant and lower significant 2 bits and therefore can reduce the number of comparators required when performing the A/D conversion of 4 bits to 6.

Also, when for example A/D conversion of 8 bits is to be carried out, as mentioned above, in the parallel type A/D converter circuit, 255 comparators are necessary, but this serial/parallel type A/D converter circuit has an advantage in that only (2⁴ -1)×2=30 comparators are sufficient to provide four upper significant bits and lower significant bits, respectively.

However, since the code conversion is carried out by two stages, during this time, it is necessary to provide a sample and hold circuit so that the input signal voltage is not changed, but is held at a fixed value, consequently leading to inducing complication of the circuit control etc.

In the above-mentioned A/D converter circuit, when increased resolution thereof is desired, a large number of taps from a voltage-division resistance element group becomes necessary, and finer processing of the semiconductor material becomes necessary. The reference voltage value of adjoining comparators becomes smaller if miniaturization is further increased, whereby a so-called offset voltage of the comparator becomes equivalent to the difference, thereby producing problems such as the loss of the comparator characteristics.

Therefore, as a means solving this problem and improving the resolution, a comparator circuit adopting a so-called interpolation construction has been proposed.

FIG. 3 is a schematic circuit diagram showing a conventional comparator circuit adopting this interpolation construction. In FIG. 3, comparators 24 and 25 denote complementary output type comparators; v_(in) denotes an input analog signal; and v_(r1), v_(r2) (v_(r1) <v_(r2)) denote reference voltages; respectively.

In this comparator circuit, an imaginary voltage at an intermediate point between two reference voltages v_(r1) and v_(r2) is obtained from the positive output of the comparator 24 and the negative output of the comparator 25, and the result of comparison of this imaginary voltage with the input analog signal v_(in) is successively obtained.

This structure has an advantage in that the error resulting from of, for example, the processing precision can be easily absorbed in comparison with a case where a large number of independent taps are adopted as mentioned above. This design however, can merely perform an equal weight between two reference voltages v_(r1) and v_(r2), and only can obtain an excessive result of comparison with the voltage at an intermediate point between two reference voltages. This design cannot freely obtain an imaginary voltage or a plurality of imaginary voltages.

Accordingly, there are problems in that the resolution of the above-mentioned conventional A/D converter circuit can be raised to only twice its level and improvement exceeding this is difficult, and furthermore, the application range is restricted.

A detailed description will be further made particularly of another design in the related art, which is a modification of the lower data encoder.

FIGS. 4A and 4B illustrate a circuit diagram showing an example of the structure of a conventional A/D converter circuit and shows a circuit structure for converting an analog signal V_(IN) to a 4-bit digital code.

In FIG. 4A, reference numeral 30 denotes a matrix circuit; 61 to 60 denote upper data comparators; 63 denotes an upper data encoder; 31 to 37 denote lower data comparators; 40 denotes a lower data encoder; 64 an inverted gate; 65 an inhibit gate; 66 a selection gate; and 67 an inverter; respectively.

The matrix circuit 30 is comprised of 28 switching blocks S_(b11) to S_(b17), S₂₁ to S_(b27), S_(b31) to S_(b37), and S_(b41) to S_(b47) arranged in the form of a matrix comprising 4 rows and 7 columns.

The switching blocks S_(b11) to S_(b17), S_(b21) to S_(b27), S_(b31) to S_(b37) and S_(b41) to S_(b47) are comprised of differential-type amplifiers comprising npn-type transistors Q₁, Q₂, and Q₃.

Except for parts, reference voltages obtained by dividing the reference voltages V_(RT) -V_(RB) by the reference resistance elements R₃₁ to R₄₆ are supplied to the base of one transistor Q₁ constituting a so-called differential pair, and the analog signal V_(IN) to be converted to the digital code is supplied to the base of the other transistor Q₂, respectively.

Also, emitters of the transistors Q₁ and Q₂ are connected to each other, and the middle point of connection thereof is connected to the current source I via the transistor Q₃ which is switched by the control signal mentioned later.

Also, a power source voltage V_(DD) is supplied to the collectors of the transistors Q₁ and Q₂ via the resistor r. The output terminals thereof are connected to the inputs to the comparators C_(D1) to C_(D7) of seven lower data comparators 31 to 37, respectively. Joint use is made of the first stage amplifiers of the lower data comparators 31 to 47.

In the figure, switching blocks S_(b11), S_(b12), S_(b16), S_(b17), S_(b21), S_(b22), S_(b26), S_(b27), S_(b31), S_(b32), S_(b36), S_(b37), S_(b41), S_(b42), S_(b46), and S_(b47) further output 2LSB redundant bits with respect to 2-bit lower data conversion code. Particularly, among them, S_(b11), S_(b12), S_(b41), and S_(b42) are given fixed input signals so that a constant binary signal "H" or "L" is output when activation is made by the control signal.

Also, particularly, a system is devised so that the collectors of the transistors Q₁ and Q₂ at the second row and fourth row of the switching block are connected to the line in an opposite direction to the collector outputs of the transistors Q₁ and Q₂ at the first row and the third row of the switching block, whereby the lines of the serially connected reference resistance elements R₁ to R₁₆ applied with the reference potentials (voltages) V_(RT) -V_(RB) can be formed by folding-back.

Each of the three upper data comparators 61, 62, and 63 is provided with the comparators C_(U5) to C_(U7), complementary-type output amplifiers CA, and AND gates A_(u5) to A_(u8), respectively.

An analog signal V_(IN) is supplied to one side inputs of the respective comparators C_(U) of the upper data comparators 61 to 63, and reference voltages V₁, V₂, and V₃ obtained by dividing the reference potentials V_(RT) to V_(RB) by the rough quantization are supplied to the other side inputs.

The outputs of the respective comparators C_(U) of the upper data comparators 61 to 63 become the level of "H" or "L" corresponding to the level of the sampled analog signal and are set so that only one of the respective AND gates A_(U) outputs the "1" level.

The output signals of the respective AND gates A_(U) are wired-connected and converted to a binary code via the upper data encoder 60. In the selection gate 66 mentioned later, correction is applied to the upper significant two bits of the codes D₁ and D₂.

Also the lower data comparators 31 to 37 are formed in the same way as the upper data comparators 61 to 63. Particularly, the lower data comparators 33, 34, and 35 further finely digitize the inside of the quantization level selected by the upper data comparator and output the lower significant 2 bits of the codes D₃ and D₄ via the lower data encoder 40.

Further, this A/D converter circuit is designed so that comparators 31, 32, 36, and 37 produce the redundant code of 2LSB which are provided on the left and right of this lower data comparator, and the code conversion operation is carried out also for the analog signal V_(IN) out of the conversion range of the lower data comparator, specified by the upper data comparators 61 to 63.

In such a structure, for example when the sampling voltage V_(S) of the sampled analog signal is represented as V_(RB) <V_(S) <V₃, the outputs of comparators C_(U) of the upper data comparators 61, 62, and 63 become all "L", so that the binary signal output, is "0" which output from the AND gates A_(u5) to A_(u7), and "1" is output from A_(u8), respectively.

As a result, a binary signal [0001] is input to the upper data encoder 63, and by a so-called wired-OR circuit, [00] is output to the first two lines [LN₅ ]; [00] is output also to the next two lines [LN₆ ], and [01] is output to the next two lines [LN₇ ].

When the sampling voltage V_(S) is represented as V₃ <V_(S) <V₂, similarly the binary signal of "0" is output from the upper data side AND gates A_(U5), A_(U6), and A_(U8), and the binary signal "1" is output from the gate A_(U7), respectively.

As a result, a binary signal such as [0010] is input to the upper data encoder 63, so that [00] is output from the line [LN₅ ]; [01] is output from the line [LN₆ ]; and [10] is output from the line [LN₇ ].

Below, the relationship between the input and output of the upper data encoder 60 including the case where V₂ <V_(S) <V₁ and V₁ <V_(S) <V_(RT) is as shown in FIG. 5.

In parallel to this, the transistors Q₃ of the respective switching blocks connected to the control lines (x₅, x₆, x₇, and x₈) at which the binary output signal has become "1", among the respective AND gates A_(U)(5, 6, 7, 8), is set to ON, and further the fine digitization of the quantization level is executed.

For example, when only the output of the AND gate A_(U7) becomes a "1" level, the transistors Q₃ of the switching blocks S_(b31) to S_(b37) turn ON, so that the reference voltage divided by the reference resistance elements R₃₇ to R₄₃ and the sampling voltage V_(S) are differentially amplified at the switching blocks S_(b31) to S_(b37) and compared by the lower data comparators 31 to 37.

Similarly, the switching blocks S_(b21) to S_(b27) are activated when the output of the AND gate A_(U6) is at the "1" level, a differential amplification operation is carried out, and the comparison by the lower data comparators 31 to 37 is carried out.

In this way, in the lower data code, the sampled voltage V_(S) and the reference voltage divided by the reference resistance element of that row are compared in units of rows of the switching block, the binary signals are output from the AND gates A_(D1) to A_(D7) and A_(D8) of the lower data comparators 31 to 37 as shown in FIG. 6, and these binary signals are encoded at the lower data encoder 40, whereby the lower significant 2 bits of the conversion codes D₃ and D₄ are output from the lower data code line [LN₁ ].

Moreover, the output levels of the selection lines LN₂, LN₃, and LN₄ are changed as shown in FIG. 6.

Then, as indicated below by a, b, and c, when a signal of the "1" level is output to either of these selection lines LN₂, LN₃, and LN₄, the upper significant 2 bits of the conversion codes D₁ and D₂ from the lines LN₅, LN₆, and LN₇ in the upper data encoder 30 are selectively output via the OR gates OR₁ and OR₂.

(a) When the conversion code with which "1" is produced in the selection line LN₃ (0 line), that is, the lower significant 2 bits of the conversion codes D₃ and D₄ become [00], [10], and [11] corresponding to the upper data conversion codes, the outputs of the AND gates A₁ and A₂ constituting the inhibit gate 65 become "0", and therefore the outputs of the AND gates A₁, A₃, A₄, and A₆ existing inside the selection gate 66 become "0".

As a result, the upper data D₁ and D₂ codes of the line [LN₆ ] output from the upper data encoder 63 are output as they are via the AND gates A₂ and A₅ of the selection gate 66 and the OR gates OR₁ and OR₂.

This case of (a) indicates a case where the level of the analog signal when performing the conversion of the upper significant 2 bits is not changed from the analog signal when performing the conversion of the lower significant 2 bits, and the correction is not carried out.

(b) Where the selection line LN₂ is "1" and the AND gate A_(U5) or A_(U7) is "1", and where the selection line LN₄ is "1" and the AND gate A_(U8) or A_(U6) is "1", the AND gate A₁ constituting the inhibit gate 65 is opened. As a result, the upper significant 2 bits of the codes D₁ and D₂ of the line LN₅ input to the AND gates A₁ and A₄ are output via the OR gates OR₁ and OR₂.

This case of (b) performs the correction where the level of the analog signal when digitizing the upper significant 2 bits D₁ and D₂ is higher than the analog signal when digitizing the lower significant 2 bits D₃ and D₄.

For example, as shown in FIG. 7, when the truth value of the sampling value V_(S) of the analog signal is V_(A), and when the conversion code of the upper significant 2 bits is erroneously output at [10] and output at a correct lower significant 2 bits of the conversion code [11] from the lower data comparator, "1" is subtracted from the upper significant 2 bits of the conversion code [10], and corrected to [01], thereby obtaining a correct code output [0111].

Namely, this case means that the control line erroneously selects the line of the switching block, but since the lower data comparator 46 on the right side detecting the redundant bit outputs [00], the upper significant 2 bits of the conversion code will be corrected.

(c) Where the selection line LN₄ is "1" and the AND gate A_(U5) or A_(U7) is "1", and where the selection line LN₂ is "1" and the AND gate A_(U8) or A_(U6) is "1", the output of the AND gate A₂ constituting the inhibit gate 65 becomes "1", and the AND gates A₃ and A₆ of the selection gate 66 are opened.

As a result, the upper significant 2 bits of the codes D₁ and D₂ of the line LN₇ input to these AND gates A₃ and A₆ are output via the OR gates OR₁ and OR₂, and "+1" is added to the upper significant 2 bits of the codes.

Namely, in this case of (c), where the sampling level of the analog signal when digitizing the upper significant 2 bits of D₁ and D₂ is lower than the quantization level range at that time, a correction is applied.

For example, when the truth value of the analog signal V_(IN) exists at the point of V_(B), when the upper significant 2 bits become [00], if the numerical value of the lower significant 2 bits is output as [00], "+1" is added to the upper significant 2 bits [00], to obtain [01], and the [0100] corresponding to the sampling voltage _(VB) of the correct analog signal is output.

This A/D converter circuit adds a comparator for detecting the redundant bit to the lower data comparator as described above, outputs, when the lower data conversion code out of the range of the upper data conversion code (region indicated by a hatching in FIG. 7), a signal of the "1" level to the selection line LN₂ or LN₄, and performs the correction of the upper data conversion code, and therefore has an advantage that a correct conversion code detected at the point of time of lower data can be obtained by high speed sampling even when the settling characteristic of the sampling circuit is poor.

As mentioned above, in the conventional circuit, for correcting the upper data code, a correction is carried out based on the concept of adding "1" and subtracting "1".

For this reason, it is constituted so that, in the upper data, normal data and lower redundant data (data obtained by subtracting "1" from the normal data) and the upper redundant data (data obtained by adding "1" to the normal data) are settled into respective groups, and one is selected from among the three groups by a selection signal from the lower data encoder.

Nevertheless, there alternately exists a column in which the right part of the resistance column becomes the lower redundancy and a column in which it becomes the upper redundancy. Accordingly, there is a case where the lower data encoder connected to the right part of the resistance column selects the lower redundant data and a case where it selects the upper redundant data.

Accordingly, the data to be selected differs for each column, and therefore the inverted gate 64 and inhibit gate 65 were necessary for controlling this.

However, the selection signal from the lower data encoder 50 (LN₂, LN₃, and LN₄ in the diagram) passes through the inverted gate 64 and the inhibit gate 65, and then is transferred to the selection gate 66, and therefore the selection signal is input to the selection gate 66 with a time lag relative to the upper data output from the upper data encoder 63.

For this reason, a delay due to the existence of the inverted gate 64 and the inhibit gate 65 occurs in the output processing of the conversion code, consequently leading to a problem that the conversion time of the A/D converter circuit is increased.

Moreover, there also exists a problem in that increases of the chip area and power consumption are induced since an excessive quantity of inverted gates and inhibit gates become necessary.

Further, there also exists another problem in that, in addition to the necessity of an excessive quantity of inverted gates and inhibit gates, three selection signals become necessary, and three sets of upper data codes to be selected become necessary too, and also the number of input gates in the selection gate is increased, and therefore resulting in increases of the chip area and power consumption.

Further, so as to obtain the upper significant "a" bits, (2^(a) -1) upper data comparators are necessary, and 2^(a) rows become necessary too also for a row of the switching block. This is one of the causes of an increase of the chip area and the power consumption.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an A/D converter circuit which provides greatly improved resolution.

Another object of the present invention is to provide an A/D converter circuit in which prevents an increase of the power consumption and chip area, but also one in which it is not necessary to provide a sampling and holding circuit, and thus the complication of the circuit control etc. can be prevented.

Still another object of the present invention is to provide an A/D converter circuit with which the increase of speed of the conversion processing, reduction of the surface area of the chip, and reduction of the power consumption can be achieved.

According to the present invention, there is provided an analog/digital converter circuit including: a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by an upper data conversion output signal in units of rows, comparing the respective reference voltages divided by the reference resistance elements with an input signal to be converted, and detecting the presence/absence of lower significant bit data and redundant bit data, thereby providing a differential output; an upper data encoder comparing the reference voltage supplied to a switching block positioned at a specific position of the switching block matrix with the input signal to be converted, and providing a plurality of conversion codes of the upper significant bits in accordance with the result of this comparison; a lower data comparator circuit including first and second comparators with weights of outputs set to N and which provides the complementary output; a third comparator with a weight of output set to n₁ and which provides the complementary output; a fourth comparator with a weight of output set to n₂ (note, n₁ +n₂ =N) and which provides the complementary output; a first adder which adds one output of said third comparator and one output of said fourth comparator; and a second adder which adds the other output of third comparator and the other output of fourth comparator, wherein a differential output of one row of the switching block being connected to the inputs of the first comparator and third comparator, and the differential output of the other row of the switching block being connected to the inputs of the second comparator and said fourth comparator; a lower data encoder, providing a predetermined lower data conversion code for the complementary outputs of the respective comparators of the lower data comparator in accordance with the presence/absence of the lower significant bit data and redundant bit data, and generating a selection signal for selecting one conversion code from among the conversion codes of the upper significant bits of the upper data encoder; and a selection gate selectively outputting one conversion code from among a plurality of conversion codes of the upper significant bits output from the upper data encoder based on the selection signal output from the lower data encoder.

Preferably, the lower data comparator circuit may include a ring comparator comprising a plurality of comparator circuit, each including a first comparator or second comparator and a third comparator and fourth comparator corresponding to respective row of the switching blocks, inputs of the respective comparators being connected to the differential outputs of the switching blocks of the corresponding row and the outputs of the third and fourth comparators of each comparator circuit being connected to the output of the third comparator or fourth comparator of the other comparator circuit. Also, the lower data comparator circuit may include a suppression circuit which cuts a predetermined position of the ring comparator in accordance with the upper data conversion output signal, and suppresses the unnecessary input of the output of the comparator to the lower data comparator.

Specifically, the weights of outputs of third and fourth comparators are set as n₁ =n₂ =N/2.

Also, according to the present invention, there is provided an analog/digital converter circuit including: a plurality of switching blocks, arranged in the form of a matrix, comparing the respective reference voltages provided by dividing said reference potential by serially connected a plurality of (n) resistance elements with an input signal to be converted; an upper data comparator comparing the reference voltage applied to the specific position of switching block in the row direction with the input signal to be converted, thereby providing the conversion code of the upper significant bit; a determining circuit determining whether the number of the switching blocks obtaining a comparison result that the level of the input signal to be converted is larger than the reference voltage level is even or odd; and a lower data encoder providing the conversion code of a lower significant bit in accordance with the result of determination of the determining circuit.

Preferably, the respective switching blocks are constituted by differential type amplifiers, each having a pair of transistors the base of which being supplied with the input signal to be converted and the divided reference voltage; and the determining circuit is constituted in that the transistor output to which the input signal is supplied and the transistor output to which the reference voltage is supplied are alternately connected for each row and are connected to a load element.

Also, preferably, the determining circuit includes a means which performs the exclusive-OR of the adjoining switching blocks for each row and outputs the total sum thereof to the lower data encoder. The determining circuit may have a plurality of exclusive-OR gates performing the exclusive-OR of the outputs of the adjoining switching blocks and constituted so that the outputs of the respective exclusive-OR gates are connected.

Preferably, the plurality of n reference resistance elements are arranged in a plurality of rows by folding-back so that the direction of application of the reference voltage becomes reverse for each predetermined number of reference resistance elements. Also, provision is made of an inverted gate which inverts, when a direction of application of voltage of a predetermined row is used as a reference, the obtained lower significant data conversion code obtained based on the reference voltage by the reference resistance elements of the row in the direction of application which is reverse to the former and outputs the same.

According to the present invention, there is further provided an analog/digital converter circuit including: a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by an upper data conversion output signal for each row, comparing the respective reference voltages divided by said reference resistance elements with an input signal to be converted, and detecting the presence/absence of the lower significant bit data and redundant bit data for each predetermined row; an upper data encoder, comparing the reference voltage at a specific portion in the row direction of the switching block with the input signal to be converted, and providing the conversion code of the upper significant bit in accordance with a redundant mode or non-redundant mode which are set in advance in accordance with the result of this comparison; a lower data encoder, providing the conversion code of the lower significant bit and the conversion code of the redundant bit out of the conversion range specified by the upper data encoder from the outputs of the respective switching blocks in accordance with the presence/absence of the lower significant bit data and the redundant bit data, and generating a selection signal in accordance with the redundant mode or non-redundant mode in accordance with the presence/absence of the redundant bit data; and a selection gate selectively outputting the conversion code of the upper significant bit in accordance with the redundant mode or non-redundant mode from among the conversion codes of the upper significant bit in accordance with the redundant mode or non-redundant mode output from the upper data encoder based on the selection signal in accordance with the mode output from the lower data encoder.

According to the present invention, there is provided an analog/digital converter circuit including: a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by the upper data conversion output signal for each row, comparing the respective reference voltages divided by reference resistance elements with an input signal to be converted, and detecting the presence/absence of the lower significant bit data and redundant bit data; at least one data change point detection circuit comparing the reference voltage generated between mutually adjoining rows excluding at least the uppermost row or lowermost row of switching block matrix with the input signal to be converted, and detecting the change point of data; an upper data encoder providing the conversion code of the upper significant bit in accordance with 2 modes set in advance in accordance with the result of detection of the data change point detection circuit; a lower data encoder dividing the outputs of the respective switching blocks in units of rows into two groups in accordance with said 2 modes, providing the predetermined lower data conversion code in accordance with the presence/absence of the lower significant bit data and redundant bit data for each of the respective divided groups, and generating a selection signal for selecting one selection code from among the two upper significant bits of conversion codes of the upper data encoder; and a selection gate selectively outputting one conversion code selected from among two upper significant bits of conversion codes output from the upper data encoder based on the selection signal output from the lower data encoder.

According to the present invention, there is provided an analog/digital converter circuit including: a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by the upper data conversion output signal for each row, comparing the respective reference voltages divided by the reference resistance elements with an input signal to be converted, and detecting the presence/absence of the lower significant bit data and redundant bit data; an upper data encoder, comparing the reference voltage applied to the specific position of the switching block in the row direction with the input signal to be converted, and providing the two conversion codes of the upper significant bit excluding the predetermined bits among the upper significant bits in accordance with the 2 modes set in advance in accordance with the result of this comparison; a lower data encoder, dividing the outputs of said respective switching blocks in units of columns into two groups in accordance with said 2 modes, providing the predetermined lower data conversion code in accordance with the lower significant bit data and the presence/absence of the redundant bit data for each of divided groups, and generating the selection signal for selecting one conversion code from among 2 upper significant bits of conversion codes of the upper data encoder; and a selection gate selectively outputting one conversion code selected from among 2 upper significant bits of conversion codes output from said upper data encoder based on the selection signal output from the lower data encoder. The selection signal is output as the predetermined bit of the upper significant conversion code excluded at the upper data encoder.

According to the present invention, there is provided an analog/digital converter circuit including: a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by the upper data conversion output signal for each row, comparing the respective reference voltages the by the reference resistance elements with an input signal to be converted, and detecting the presence/absence of the lower significant bit data and redundant bit data; an upper data encoder, comparing the reference voltage applied to the specific position of switching block in the row direction with the input signal to be converted, and providing the conversion code of the upper significant bit in accordance with the 2 modes set in advance in accordance with the result of this comparison; a lower data encoder dividing the outputs of said respective switching blocks in units of columns into two groups in accordance with 2 modes, providing the predetermined lower data conversion code in accordance with the lower significant bit data and the presence/absence of the redundant bit data for each of divided groups, and generating the selection signal for selecting one conversion code from among 2 upper significant bits of conversion codes of the upper data encoder; and a selection gate selectively outputting one conversion code selected from among 2 upper significant bits of conversion codes output from the upper data encoder based on the selection signal output from the lower data encoder.

According to the present invention, there is provided an analog/digital converter circuit including: a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by the upper data conversion output signal for each row, comparing the respective reference voltages divided by the reference resistance elements with an input signal to be converted, and detecting the presence/absence of the lower significant bit data and redundant bit data; an upper data encoder comparing the reference voltage supplied to the switching block positioned intermediate in the rows excluding at least the uppermost row or lowermost row with the input signal to be converted, and providing the conversion code of the upper significant bit in accordance with the 2 modes set in advance in accordance with the result of this comparison; a lower data encoder dividing the outputs of said respective switching blocks in units of columns into two groups in accordance with the 2 modes, providing the predetermined lower data conversion code in accordance with the lower significant bit data and the presence/absence of the redundant bit data for each of divided groups, and generating the selection signal for selecting one conversion code from among 2 upper significant bits of conversion codes of the upper data encoder; and a selection gate selectively outputting one conversion code selected from among 2 upper significant bits of conversion codes output from the upper data encoder based on the selection signal output from the lower data encoder.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and features and other objects and features of the present invention will be described more in detail with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a serial/parallel A/D converter of a first related art;

FIG. 2 is a timing chart of the A/D converter shown in FIG. 1;

FIG. 3 is a view of a comparator used for the comparator of the A/D converter etc. of a second related art;

FIGS. 4A and 4B are a circuit diagram of another serial/parallel A/D converter of a third related art;

FIG. 5 and FIG. 6 show logical values of the A/D converter shown in FIG. 4;

FIG. 7 is an explanatory view of the operation of the A/D converter shown in FIG. 5;

FIGS. 8A and 8B are a block diagram of a serial/parallel A/D converter of a first embodiment of the present invention;

FIG. 9 is a structural view of the comparator of a second embodiment of the present invention;

FIG. 10 is an explanatory view of the comparator shown in FIG. 9;

FIG. 11 is a structural view of an A/D converter of a third embodiment of the present invention;

FIG. 12 shows the logical value of the A/D converter shown in FIG. 11;

FIG. 13 is a block diagram of a serial/parallel A/D converter of a fourth embodiment of the present invention;

FIG. 14A to FIG. 14C are structural views of the circuit of the switching block of the A/D converter shown in FIG. 13;

FIG. 15 and FIG. 16 are views showing input/output characteristics of the A/D converter shown in FIG. 13;

FIG. 17 is a block diagram of a serial/parallel A/D converter of a fifth embodiment of the present invention;

FIG. 18 shows the operation of the A/D converter shown in FIG. 17;

FIGS. 19A and 19B are a block diagram of a serial/parallel A/D converter of a sixth embodiment of the present invention;

FIG. 20 and FIG. 21 show the logical values of the respective blocks for explaining the operation of the A/D converter shown in FIG. 19;

FIGS. 22A-22C are block diagrams of a serial/parallel A/D converter of a seventh embodiment of the present invention;

FIG. 23 and FIG. 24 show the logical values for explaining the logical value and redundancy of the A/D converter shown in FIG. 22;

FIGS. 25A-25C are block diagrams of a serial/parallel A/D converter of an eighth embodiment of the present invention;

FIGS. 26A-26C are block diagrams of a serial/parallel A/D converter of a ninth embodiment of the present invention;

FIG. 27 and FIG. 28 are views of showings the logical values for explaining the operation concerning the redundancy of the A/D converter shown in FIG. 26;

FIGS. 29A-29C are block diagrams of a serial/parallel A/D converter of a 10-th embodiment of the present invention;

FIGS. 30A-30C are block diagrams of a serial/parallel A/D converter of an 11th embodiment of the present invention;

FIG. 31 and FIG. 32 are views showing the logical values for explaining the operation concerning the redundancy of the A/D converter shown in FIG. 30;

FIGS. 33A-33C are block diagrams of a serial/parallel A/D converter of a 12-th embodiment the present invention;

FIGS. 34A and 34B are a block diagram of a serial/parallel A/D converter of a 13th embodiment of the present invention;

FIG. 35 and FIG. 36 are vies showing the logical values for explaining the operation of the A/D converter shown in FIG. 34;

FIGS. 37A and 37B are a block diagram of a serial/parallel A/D converter of a 14th embodiment of the present invention; and

FIGS. 38A and 38B are a block diagram of a serial/parallel A/D converter of a 15th embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be explained in detail referring to the drawings.

An explanation will be made of a first embodiment of the present invention.

FIG. 8 is a circuit diagram showing one embodiment of an A/D converter circuit according to the present invention.

Reference numeral 100 denotes a matrix circuit; 151 to 153 denote upper data comparators; 130, an upper data encoder; 141, a selection gate; 142, an inverter; 101 to denote interpolation-type lower data comparators; 111 to 118 denote latch circuits; 121 and 122 denote suppression circuits; 130, a lower data side AND gate circuit; 140, a lower data encoder; R₁ to R₁₆ denote reference resistance elements; r denotes a resistance element for a load; B_(U1) to B_(U3) and B_(D0) to B_(D33) denote multiple output pin buffers; AD_(U1) to AD_(U5) denote 2-input AND gates on the upper data side; and OR₁ denotes a 2-input OR gate for the conversion code output; respectively.

The present circuit shows a circuit configuration for converting the input analog signal V_(IN) to 6 bits of a digital code.

The positive outputs of the comparators CU₉ of the upper data comparator 151 are connected to the two inputs of the 2-input AND gates AD_(U9), and the negative outputs are connected to one input of the AND gate AD_(U9).

The positive output of the comparator CU₁₀ of the upper data comparator 152 is connected to both inputs of the 2-input AND gate AD_(U10), and the negative output is connected to the two inputs of the AND gate AD_(U4).

The positive output of the comparators CU₁₁ of the upper data comparator 153 is connected to the other input of the 2-input AND gates AD_(U11), and the negative output is connected to the two inputs of the AND gate AD_(U5).

The output of the AND gate AD_(U9) is supplied as the control signal x₁ to the base of the transistor Q₃ of the switching blocks S_(C12), S_(C14), S_(C16), and S_(C18) ; the output of the AND gate AD_(U10) is supplied as the control signal x₂ to the base of the transistor Q₃ of the switching blocks S_(C21), S_(C23), S_(C25), and S_(C27) ; the output of the AND gate AD_(U11) is supplied as the control signal x₃ to the base of the transistor Q₃ of the switching blocks S_(C32), S_(C34), S_(C36), and S_(C38) ; the output of the AND gate AD_(U12) is supplied as the control signal x₄ to the base of the transistor Q₃ of the switching blocks S_(C41), S_(C43), S_(C45), and S_(C47) ; and the output of the AND gate AD_(U13) is supplied as the control signal x₁₅ to the base of the transistor Q₁₀₃ of the switching blocks S_(C52), S_(C54), S_(C56), and S_(C58).

In these AND gates AD_(U9) to AD_(U13), the mutually adjoining two output levels simultaneously become "1".

Concretely, the binary output signal levels of the AND gates AD_(U9) and AD_(U10), AD_(U10) and AD_(U11), AD_(U11) and AD_(U12), and AD_(U12) and AD_(U13) simultaneously become "1", the transistors Q₃ of the respective switching blocks of the matrix circuit 100 connected to the control lines (x₁₁, x₁₂, x₁₃, x₁₄, and x₁₅) which have become the "1" level are controlled to turn ON in units of two rows, and the fine digitization of the quantization level is carried out.

The lower data comparators 101 to 108 are respectively constituted by comparators C_(N1) with gains which are set to N, comparators C_(N1) with gains which are set to n₁ (n₁ <N), and comparators C_(n1) with gains which are set to n₂ (note, n₁ =n₂ <N, n₁ +n₂ =N).

The collector outputs of the transistors Q₁ of the switching blocks S_(C21) and S_(C41) at the first column of the matrix circuit 10 are supplied to one side inputs of the comparators C_(N1), C_(n1), and C_(n2) of the lower data comparator 101, and the collector outputs (differential outputs) of the transistors Q₂ of the switching blocks S_(C21) and S_(C41) are supplied to the other side inputs.

The collector outputs of the transistors Q₁ of switching blocks S_(C12), S_(C32), and S_(C52) at the second column of the matrix circuit 10 are supplied to one side inputs of the respective comparators C_(N1), C_(n1), and C_(n2) of the lower data comparator 102, and the collector outputs (differential outputs) of the transistors Q₁₀₂ of the switching blocks S_(C12), S_(C32), and S_(C52) are supplied to the other side inputs.

The collector outputs of the transistors Q₁ of the switching blocks Sc23 and Sc43 at the third column of the matrix circuit 10 are supplied to one side inputs of the respective comparators C_(N1), C_(n1), and C_(n2) of the lower data comparator 103, and the collector outputs (differential outputs) of the transistors Q₁₀₂ of the switching blocks S_(C23) and S_(C43) are supplied to the other side inputs.

The collector outputs of the transistors Q₁ of the switching blocks S_(C14) and S_(C34) at the fourth column of the matrix circuit 10 are supplied to one side inputs of the respective comparators C_(N1), C_(n1), and C_(n2) of the lower data comparator 104, and the collector outputs (differential outputs) of the transistors Q₁₀₂ of the switching blocks S_(C14) and S_(C34) are supplied to the other side inputs.

The collector outputs of the transistors Q₁₀₁ of the switching blocks S_(C25) and S_(C45) at the fifth column of the matrix circuit 10 are supplied to one side inputs of the respective comparators C_(N1), C_(n1), and C_(n2) of the lower data comparator 105, and the collector outputs (differential outputs) of the transistors Q₁₀₂ of the switching blocks S_(C25) and S_(C45) are supplied to the other side inputs.

The collector outputs of the transistors Q₁₀₁ of the switching blocks S_(C16) and S_(C36) at the sixth column of the matrix circuit 10 are supplied to one side inputs of the respective comparators C_(N1), C_(n1), and C_(n2) of the lower data comparator 106, and the collector outputs (differential outputs) of the transistors Q₁₀₂ of the switching blocks S_(C16) and S_(C36) are supplied to the other side inputs.

The collector outputs of the transistors Q₁ of the switching blocks S_(C27) and S_(C47) at the seventh column of the matrix circuit 10 are supplied to one side inputs of the respective comparators C_(N1), C_(n1), and C_(n2) of the lower data comparator 107, and the collector outputs (differential outputs) of the transistors Q₁₀₂ of the switching blocks S_(C27) and S_(C47) are supplied to the other side inputs.

The collector outputs of the transistors Q₁₀₁ of switching blocks S_(C18) and S_(C38) at the eighth column of the matrix circuit 10 are supplied to one side inputs of the respective comparators C_(N1), C_(n1), and C_(n2) of the lower data comparator 108, and the collector outputs (differential outputs) of the transistors Q₁₀₂ of the switching blocks S_(C18) and S_(C38) are supplied to the other side inputs.

The two outputs on the positive side and negative side of the respective comparators C_(N1), C_(n1), and C_(n2) of the lower data comparators 101 to 108 are connected to the load resistance element r which is connected to the ground level and, at the same time, connected to the respective latch circuits 111 to 118 and lower data comparators corresponding to the adjoining columns or corresponding to every other column.

Namely, the two outputs on the positive side and negative side of the comparator C_(N1) of the lower data comparator 101 are connected to the latch circuit 111. The positive side and negative side outputs of the comparator C_(n1) of the lower data comparator 101 are connected to the latch circuit 111 and, at the same time, the positive side output is connected to the positive side output of the comparator C_(n1) of the lower data comparator 102, and the negative side output is connected to the negative side output of the comparator C_(n1) of the lower data comparator 102. The positive side and negative side outputs of the comparator C_(n2) of the lower data comparator 101 are connected to the latch circuit 111 and, at the same time, connected to the positive side output of the comparator C_(n1) of the lower data comparator 103, and the negative side output is connected to the negative side output of the comparator C_(n1) of the lower data comparator 103.

The two outputs on the positive side and negative side of the comparator C_(N1) of the lower data comparator 102 are connected to the latch circuit 112, and the positive output of the comparator C_(n1) is connected to the latch circuit 112. The positive side and negative side outputs of the comparator C_(n2) of the lower data comparator 102 are connected to the latch circuit 112 and, at the same time, the positive side output is connected to the positive side output of the comparator C_(n1) of the lower data comparator 104, and the negative side output is connected to the negative side output of the comparator C_(n1) of the lower data comparator 104.

The two outputs on the positive side and negative side of the comparators C_(N1) and C_(n1) of the lower data comparator 103 are connected to the latch circuit 113. The positive side output of the comparator C_(n2) of the lower data comparator 103 is connected to the latch circuit 113, and, connected to the positive side output of the comparator C_(n1) of the lower data comparator 105, and the negative side output is connected to the negative side output of the comparator C_(n1) of the lower data comparator 105.

The two outputs on the positive side and negative side of the comparator C_(N1) of the lower data comparator 104 are connected to the latch circuit 114, and the positive output of the comparator C_(n1) is connected to the latch circuit 114. The positive side and negative side outputs of the comparator C_(n2) of the lower data comparator 104 are connected to the latch circuit 114 and, at the same time, the positive side output is connected to the positive side output of the comparator C_(n1) of the lower data comparator 106, and the negative side output is connected to the negative side output of the comparator C_(n1) of the lower data comparator 106.

The two outputs on the positive side and negative side of the comparators C_(N1) and C_(n1) of the lower data comparator 105 are connected to the latch circuit 115. The positive side output of the comparator C_(n2) of the lower data comparator 105 is connected to the latch circuit 115, and, connected to the positive side output of the comparator C_(n1) of the lower data comparator 107, and the negative side output is connected to the negative side output of the comparator C_(n1) of the lower data comparator 107.

The two outputs on the positive side and negative side of the comparator C_(N1) of the lower data comparator 106 are connected to the latch circuit 116, and the positive output of the comparator C_(n1) is connected to the latch circuit 116. The positive side and negative side outputs of the comparator C_(n2) of the lower data comparator 106 are connected to the latch circuit 116 and, at the same time, the positive side output is connected to the positive side output of the comparator C_(n1) of the lower data comparator 108, and the negative side output is connected to the negative side output of the comparator C_(n1) of the lower data comparator 108.

The two outputs on the positive side and negative side of the comparators C_(N1) and C_(n1) of the lower data comparator 107 are connected to the latch circuit 117. The positive side output of the comparator C_(n2) of the lower data comparator 107 is connected to the latch circuit 117 and, at the same time, connected to the positive side output of the comparator C_(n2) of the lower data comparator 108, and the negative side output is connected to the negative side output of the comparator C_(n2) of the lower data comparator 108.

The two outputs on the positive side and negative side of the comparators C_(N1) and C_(n2) of the lower data comparator 108 are connected to the latch circuit 118 and, at the same time, the positive side output of the comparator C_(n1) is connected to the latch circuit 118.

In this way, the outputs of the comparators C_(n1) and C_(n2) of the lower data comparators 101 to 108 having gains _(n1) and _(n2) are connected to the comparator C_(n1) or C_(n2) of the lower data comparators corresponding to respective adjoining columns or corresponding to every other column, and a comparison circuit having an interpolation construction is constituted by two comparators C_(N1) of a gain N and comparators C_(n1) and C_(n2) having gains n1 and n2, of the connected two lower data comparators.

Below, a detailed explanation will be made of the fundamental structure of the comparison circuit having an interpolation construction constituted between two lower data comparators, and the function thereof using FIG. 9 and FIG. 10.

FIG. 9 is a structural block diagram showing the fundamental structure of the present comparison circuit of a second embodiment of the present invention.

In FIG. 9, CMP₁ (161) denotes a first comparator; CMP₂ (162) denotes a second comparator; CMP₃ (163), a third comparator; CMP₄ (164), a fourth comparator; ADD₁, a first adder; ADD₂, a second adder; V_(IN), an input analog signal (hereinafter simply referred to as an input signal); V_(R1), a first reference voltage; V_(R2), a second reference voltage; and A to E denote comparison outputs; respectively.

The first comparator CMP₁ (161) is constituted by a 2-input and 2-output differential amplifier obtaining a complementary output, for example, the weight of the output of which, that is, the gain of which, being set to N times, one side input terminals of which being connected to the input line of the input signal V_(IN), and the other side inputs of which being connected to the input line of the first reference voltage V_(R1).

The first comparator CMP₁ (161) compares the input signal V_(IN) with the first reference voltage V_(R1), outputs the signal S₇₁ from the negative output, and outputs the signal S₇₂ from the positive output, respectively.

The output A of the comparison circuit is constituted by the positive and negative outputs of this first comparator CMP₁ (161).

The second comparator CMP₂ (162) is constituted by a 2-input and 2-output differential amplifier obtaining a complementary output, for example, the weight of the output of which being set to N, one side input terminals of which being connected to the input line of the input signal V_(IN), and the other side inputs of which being connected to the input line of the second reference voltage V_(R2).

The second comparator CMP₂ (162) compares the input signal V_(IN) with the second reference voltage V_(R2), outputs the signal S₇₃ from the negative output, and outputs the signal S₇₄ from the positive output, respectively.

The output E of the comparison circuit is constituted by the positive and negative outputs of this second comparator CMP₂ (162).

The third comparator CMP₃ (163) is constituted by a 2-input and 2-output differential amplifier obtaining a complementary output, for example, the weight of the output of which being set to n₁ (n₁ <N), one side input terminals of which being connected to the input line of the input signal V_(IN), and the other side inputs of which being connected to the input line of the first reference voltage V_(R1).

The third comparator CMP₃ (163) compares the input signal V_(IN) with the first reference voltage V_(R1), outputs the signal S₇₅ from the negative output, and outputs the signal S₇₆ from the positive output, respectively.

The fourth comparator CMP₄ (164) is constituted by a 2-input and 2-output differential amplifier obtaining a complementary output, for example, the weight of the output of which being set to n₂ (note, n₂ <N, n₁ +n₂ =N), one side input terminals of which being connected to the input line of the input signal V_(IN), and the other side inputs of which being connected to the input line of the second reference voltage V_(R2).

The fourth comparator CMP₄ (164) compares the input signal V_(IN) with the second reference voltage V_(R2), outputs the signal S₇₇ from the negative output, and outputs the signal S₇₈ from the positive output, respectively.

The first adder ADD₁ finds the sum (S₇₅ +S₇₇) of the negative output signal S₇₅ of the third comparator CMP₃ (163) and the negative output signal S₇₇ of the fourth comparator CMP₄ (164) and outputs the same as the signal S₇₉.

The second adder ADD₂ calculates the sum (S₇₆ +S₇₈) of the positive output signal S₇₆ of the third comparator CMP₃ (163) and the positive output signal S₇₈ of the fourth comparator CMP₄ (164). and outputs the same as the signal S₈₀.

The output C of the comparison circuit is constituted by the output signals S₇₉ and S₈₀ of these first and second adders ADD₁ and ADD₂.

Also, the output B of the comparison circuit is constituted by the output signal S₇₉ of the first adder ADD₁ and the positive output signal S₇₂ of the first comparator CMP₁ (161), and the output D of the comparison circuit is constituted by the output signal S₈₀ of the second adder ADD₂ and the negative output signal S₇₃ of the second comparator CMP₂ (162).

As mentioned above, in the present comparison circuit, the output of the third comparator CMP₃ (163) and the output of the fourth comparator CMP₄ are subjected to the weight of n₁ :n₂, and when the two are added, n₁ +n₂ (=N) is obtained, and the gain is set so that the same weight as that for the outputs of the first and second comparators CMP₁ (161) and CMP₂ (162) is obtained.

Also, the outputs CA to CE of the present comparison circuit are connected to the not illustrated latch circuit.

Here, an explanation will be made of the input/output characteristics of the respective parts of the circuit of FIG. 9 using FIG. 10.

Note that, in FIG. 10, an abscissa represents an input voltage, and an ordinate represents a relative output level, respectively.

First, the output signal S₇₉ of the first adder ADD₁ will be considered.

The signal S₇₉ is the sum of the negative output signal S₇₅ of the third comparator CMP₃ (163) and the negative output signal S₇₇ of the fourth comparator CMP₄ (164).

    S.sub.79 =S.sub.75 +S.sub.77                               (1)

Here, for the first comparator CMP₁ (161) and the third comparator CMP₃ (163), the same voltage is supplied to the two inputs thereof, respectively and, the weight of outputs of the both is N:n₁. Therefore, the following relationship equation is established between the negative output signals S₇₁ and S₇₅.

    N:n.sub.1 =S.sub.71 :S.sub.75                              (2)

From this equation (2), the signal S₇₅ can be represented as in the following equation.

    S.sub.75 =(n.sub.1 /N)·S.sub.71                   (3)

Similarly, for the second comparator CMP₂ (162) and the fourth comparator CMP₄ (164), the same voltage is supplied to the two inputs thereof, respectively and the weight of outputs of the two is N:n₂. Therefore, the following relationship is established between the negative output signals S₇₃ and S₇₇.

    N:n.sub.2 =S.sub.73 :S.sub.77                              (4)

From this equation (4), the signal S₇₇ can be represented as in the following equation.

    S.sub.77 =(n.sub.2 /N)·S.sub.73                   (5)

Accordingly, by substituting the above-described equations (3) and (5) into equation (1), equation (1) can be rewritten as follows:

    S.sub.79 =(n.sub.1 /N)·S.sub.71 +(n.sub.2 /N)·S.sub.73(6)

When considering equation (6) using FIG. 10, it represents that the signal S₇₉ becomes the line obtained by interior division of the signal S₇₁ and signal S₇₃ to n₁ :n₂.

Next, consideration will be made of the output signal S₈₀ of the second adder ADD₂.

The signal S₈₀ is the sum of the positive output signal S₇₆ of the third comparator CMP₃ (163) and the positive output signal S₇₈ of the fourth comparator CMP₄ (164).

    S.sub.80 =S.sub.76 +S.sub.78                               (7)

As mentioned above, for the first comparator CMP₁ (161) and the third comparator CMP₃ (163), the same voltage is supplied to the two inputs thereof, and the weight of outputs of the two is N:n₁, and therefore the following relationship is established between the positive output signals S₇₂ and S₇₆.

    N:n.sub.1 =S.sub.72 :S.sub.76                              (8)

From this equation (8), the signal S₇₆ can be represented as in the following equation.

    S.sub.76 =(n.sub.1 /N)·S.sub.72                   (9)

Similarly, for the second comparator CMP₂ (162) and the fourth comparator CMP₄ (164), the same voltage is supplied to the two inputs thereof, respectively, and the weight of outputs of the two is N:n₂, and therefore the following relationship is established between the positive output signals S₇₄ and S₇₈.

    N:n.sub.2 =S.sub.74 :S.sub.78                              (10)

From this equation (10), the signal S₇₀ can be represented as in the following equation.

    S.sub.78 =(n.sub.2 /N)·S.sub.74                   (11)

Accordingly, by substituting the above-described equations (9) and (10) into equation (7), equation (7) can be rewritten as follows:

    S.sub.80 =(n.sub.1 /N)·S.sub.72 +(n.sub.2 /N)·S.sub.74(12)

When considering equation (12) using FIG. 3, it represents that the signal S₈₀ becomes the line obtained by interior division of the signal S₇₂ and signal S₇₄ to n₁ :n₂.

By the result of consideration of the above-mentioned equations (6) and (12), in FIG. 10, the cross point P₂ between the signal S₇₉ and signal S₈₀ is the point obtained by interior division of the cross point P₁ between the signal S₇₁ and S₇₂ and the cross point P₃ between the signal S₇₃ and the signal S₇₄ to n₁ :n₂.

Accordingly, the output signals C (S₇₉, S₈₀) comprising the signal S₇₉ and the signal S₈₀ become the results of comparison between the input signal voltage and the imaginary voltage V_(C) indicated by the next equation.

    V.sub.C =V.sub.R1 +(V.sub.R2 -V.sub.R1)·(n.sub.1 /N)(13)

where, N=n₁ +n₂

Also, the level of the output signals B (S₇₂, S₇₉) comprising the signal S₇₂ and the signal S₇₉ change according to whether P₄, which is the cross point of the two, is high or low.

The cross point P₄ between the signal S₇₂ and the signal S₇₉ is a point of interior division of the cross point P₁ between the signal S₇₁ and signal S₇₂ and the cross point P₂ between the signal S₇₉ and signal S₈₀ to 1:1.

Accordingly, the output signals B (S₇₂, S₇₉) comprising the signal S₇₂ and the signal S₇₉ become the results of comparison between the input signal voltage and the imaginary voltage V_(B) indicated by the following equation:

    V.sub.B =V.sub.R1 +(V.sub.R2 -V.sub.R1)·(n.sub.1 /2N)(14)

Similarly, the level of the output signals D (S₇₃, S₈₀) comprising the signal S₇₃ and the signal S₈₀ change according to whether P₅ which is the cross point of the two is high or low.

The cross point P₅ between the signal S₇₃ and the signal S₈₀ is a point of interior division of the cross point P₂ between the signal S₇₉ and signal S₈₀ and the cross point P₃ between the signal S₇₃ and the signal S₇₄ to 1:1.

Accordingly, the output signals D (S₇₃, S₈₀) comprising the signal S₇₃ and the signal S₈₀ become the results of comparison between the input signal voltage and the imaginary voltage V_(D) indicated by the following equation:

    V.sub.D =V.sub.R2 -(V.sub.R2 -V.sub.R1)·(n.sub.2 /2N)(15)

As mentioned above, the present comparison circuit can obtain the result of comparison of the three interpolation points P₂, P₄, and P₅ from the two reference voltages V_(R1) and V_(R2).

The imaginary voltages V_(C), V_(B), and V_(D) at the respective interpolation points P₂, P₄, and P₅ satisfy the following relationships from the above-described equations (13) to (15) and FIG. 10:

    V.sub.R1 <V.sub.B, V.sub.C, V.sub.D <V.sub.R2              (16)

Also, it is possible to set the weights n₁ and n₂ of the outputs of the third and fourth comparators CMP₃ and CMP₄ to any value so long as it satisfies the condition of n₁ +n₂ =N.

Accordingly, by appropriately selecting the values of n₁ and n₂, the values of the respective imaginary voltages V_(B), V_(C), and V_(D) can be set to any values between the first reference voltage V_(R1) and the second reference voltage V_(R2).

For example, where it is assumed that n₁ =n₂ =N/2 as in the present embodiment,

V_(C) =V_(R1) +(V_(R2) -V_(R1))·(1/2) is obtained from equation (13);

V_(B) =V_(R1) +(V_(R2) -V_(R1))·(1/4) is obtained from equation (14); ##EQU1## is obtained from equation (15).

They represent that the result of comparison between the imaginary voltage, obtained by dividing the voltages of V_(R1) and V_(R2) by four, and the input signal.

Where the comparison circuit having such an interpolation construction is applied to the A/D converter circuit, the weights n₁ and n₂ of the outputs of the third and fourth comparators CMP₃ (163) and CMP₄ (164) desirably satisfy the condition of n₁ =n₂ =N/2.

In the structure of FIG. 8, as mentioned above, a comparison circuit is constructed having an interpolation construction wherein two interpolation outputs are obtained by two comparators C_(N1) of the gain N and the comparators C_(n1) and C_(n2) of the gains n₁ and n₂ of the two lower data comparators.

For example, the first comparator CMP₁ (161) and the third comparator CMP₃ (163) of FIG. 9 are constituted by the comparators C_(N1) and C_(n1) of the lower data comparator 101, respectively; and the second comparator CMP₂ (162) and the fourth comparator CMP₄ (164) of FIG. 9 are constituted by the comparators C_(N1) and C_(n1) of the lower data comparator 102, respectively. They function as the comparison circuits of FIG. 9. Note, as the output of the comparison circuit in this case, outputs corresponding to outputs CA, CC, and CE in FIG. 8 are obtained.

Similarly, the first comparator CMP₁ (161) and the third comparator CMP₃ (163) of FIG. 9 are constituted by the comparators C_(N1) and C_(n1) of the lower data comparator 101, respectively; and the second comparator CMP₂ (162) and the fourth comparator CMP₄ (164) of FIG. 9 are constituted by the comparators C_(N1) and C_(n1) of the lower data comparator 103, respectively. They function as the comparison circuits of FIG. 9.

Below, the first comparator CMP₁ (161) and the third comparator CMP₃ (163) of FIG. 9 are constituted by the comparators C_(N1) and C_(n1) of the lower data comparator 102, respectively; and the second comparator CMP₂ (162) and the fourth comparator CMP₄ (164) of FIG. 9 are constituted by the comparators C_(N1) and C_(n1) of the lower data comparator 104, respectively. They function as the comparison circuits of FIG. 9.

The first comparator CMP₁ (161) and the third comparator CMP₃ (163) of FIG. 9 are constituted by the comparators C_(N1) and C_(n2) of the lower data comparator 103, respectively; and the second comparator CMP₂ (162) and the fourth comparator CMP₄ (164) of FIG. 9 are constituted by the comparators C_(N1) and C_(n1) of the lower data comparator 105, respectively. They function as the comparison circuits of FIG. 9.

The first comparator CMP₁ (161) and the third comparator CMP₃ (163) of FIG. 9 are constituted by the comparators C_(N1) and C_(n2) of the lower data comparator 104, respectively; and the second comparator CMP₂ (162) and the fourth comparator CMP₄ (164) of FIG. 9 are constituted by the comparators C_(N1) and C_(n1) of the lower data comparator 106, respectively. They function as the comparison circuits of FIG. 9.

The first comparator CMP₁ (161) and the third comparator CMP₃ (163) of FIG. 9 are constituted by the comparators C_(N1) and C_(n2) of the lower data comparator 105, respectively; and the second comparator CMP₂ (162) and the fourth comparator CMP₄ (164) of FIG. 9 are constituted by the comparators C_(N1) and C_(n1) of the lower data comparator 107, respectively. They function as the comparison circuits of FIG. 9.

The first comparator CMP₁ (161) and the third comparator CMP₃ (163) of FIG. 9 are constituted by the comparators C_(N1) and C_(n2) of the lower data comparator 106, respectively; and the second comparator CMP₂ (162) and the fourth comparator CMP₄ (164) of FIG. 9 are constituted by the comparators C_(N1) and C_(n1) of the lower data comparator 108, respectively. They function as the comparison circuits of FIG. 9.

The first comparator CMP₁ (161) and the third comparator CMP₃ (163) of FIG. 9 are constituted by the comparators C_(N1) and C_(n1) of the lower data comparator 107, respectively; and the second comparator CMP₂ (162) and the fourth comparator CMP₄ (164) of FIG. 9 are constituted by the comparators C_(N1) and C_(n1) of the lower data comparator 108, respectively. They function as the comparison circuits of FIG. 9.

Note that, in these respective comparison circuits, their functions per se do not change even if the positions of the first and third comparators and the second and fourth comparators are inverted.

The latch circuits 111 to 118 are constituted by the 2-input and 2-output amplifiers a to d, respectively.

The suppression circuit 121 is constituted by the OR gates OR_(D1) and OR_(D2) and the AND gates AD_(D1) to AD_(D3), and the suppression circuit 122 is constituted by the OR gates OR_(D3) and OR_(D4) and the AND gates AD_(D4) to AD_(D6).

The AND gate circuit 130 is constituted by inverters I₁ (AD₀) and I₂ (AD₃₃) and AND gates AD₁ to AD₃₂.

In the structure of FIG. 8, a so-called ring comparator is constituted by these latch circuits 111 to 118, suppression circuits 121 and 122, the AND gate 130, and the lower data comparators 101 to 108 and constituted so that only either one of the inverters I₁ (AD₀) and I₂ (AD₃₃) and AND gates AD₁ to AD₃₂ outputs of the AND gate circuit 155 outputs the active "1" level.

Below, an explanation will be made of the configuration of connection between the outputs of the lower data comparators 101 to 108 and the latch circuits 111 to 118 and the connection configuration between the outputs of the latch circuits 111 to 118, the suppression circuits 121 and 122, and the AND gate circuit 155.

The positive output of the comparator C_(n1) of the lower data comparator 101 is connected to one input of the amplifier a of the latch circuit 111, and the negative output is connected to the other input of the amplifier a and one input of the amplifier b.

The positive output of the comparator C_(N1) of the lower data comparator 101 is connected to the other input of the amplifier b and one input of the amplifier c of the latch circuit 111, and the negative output is connected to the other input of the amplifier c and one input of the amplifier d. The positive output of the comparator C_(n2) of the lower data comparator 101 is connected to the other input of the amplifier d of the latch circuit 111.

The positive output of the amplifier a of the latch circuit 111 is connected to one input of the AND gate AD₁ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD_(D1) of the suppression circuit 121; the positive output of the amplifier b is connected to one input of the AND gate AD₂ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD_(D2) of the suppression circuit 121; the positive output of the amplifier c is connected to one input of the AND gate AD₃ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD_(D3) of the suppression circuit 121 and one input of the OR gate OR_(D1) ; and the positive output of the amplifier d is connected to one input of the AND gate AD₄ of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD₃ of the AND gate circuit 155.

To other inputs of the AND gates AD_(D1) to AD_(D3) and the OR gate OR_(D1) of the suppression circuit 121, the outputs of the inverter 142 inverting the output level of the upper data side other output buffers B_(U1) and B_(U3) (AND gates A_(U1) and A_(U3) of the upper data comparators 151 and 153) are connected.

The output of the OR gate OR_(D1) is connected to the input of the inverter I₁ of the AND gate circuit 155; the output of the AND gate AD_(D1) is connected to one input of the AND gate AD₅ of the AND gate circuit 155; the output of the AND gate AD_(D2) is connected to the other input of the AND gate AD₁ of the AND gate circuit 155; and the output of the AND gate AD_(D3) is connected to the other input of the AND gate AD₂ of the AND gate circuit 155.

The positive output of the comparator C_(n1) of the lower data comparator 102 is connected to one input of the amplifier d of the latch circuit 112. The positive output of the comparator C_(N1) of the lower data comparator 102 is connected to one input of the amplifier b of the latch circuit 112 and one input of the amplifier c, and the negative output is connected to the other input of the amplifier c and the other input of the amplifier d. The positive output of the comparator C_(n2) of the lower data comparator 102 is connected to one input of the amplifier a of the latch circuit 112, and the negative output is connected to the other input of the amplifier a and the other input of the amplifier b.

The positive output of the amplifier d of the latch circuit 112 is connected to the other input of the AND gate AD₅ of the AND gate circuit 155, and the negative output is connected to one input of the OR gate OR_(D2) of the suppression circuit 121; the positive output of the amplifier c is connected to one input of the AND gate AD₆ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD₇ of the AND gate circuit 155; the positive output of the amplifier b is connected to the other input of the AND gate AD₇ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD₈ of the AND gate circuit 155; and the positive output of the amplifier a is connected to the other input of the AND gate AD₈ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD₁₃ of the AND gate circuit 155.

To the other input of the OR gate OR_(D2) of the suppression circuit 121, the outputs of the upper data side buffers B_(U1) and B_(U3) (AND gates A_(U1) and A_(U3) of the upper data comparators 151 and 153) are connected.

The output of the OR gate OR_(D1) is connected to the other input of the AND gate AD₆ of the AND gate circuit 155.

The positive output of the comparator C_(n1) of the lower data comparator 103 is connected to one input of the amplifier a of the latch circuit 113, and the negative output is connected to the other input of the amplifier a and one input of the amplifier b. The positive output of the comparator C_(N1) of the lower data comparator 103 is connected to the other input of the amplifier b of the latch circuit 113 and one input of the amplifier c, and the negative output is connected to the other input of the amplifier c and one input of the amplifier d. The positive output of the comparator C_(n2) of the lower data comparator 103 is connected to the other input of the amplifier d of the latch circuit 113.

The positive output of the amplifier a of the latch circuit 113 is connected to one input of the AND gate AD₉ of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD₄ of the AND gate circuit 155; the positive output of the amplifier b is connected to one input of the AND gate AD₁₀ of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD₉ of the AND gate circuit 155; the positive output of the amplifier c is connected to one input of the AND gate AD₁₁ of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD₁₀ of the AND gate circuit 155; and the positive output of the amplifier d is connected to one input of the AND gate AD₁₂ of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD₁₁ of the AND gate circuit 155.

The positive output of the comparator C_(n1) of the lower data comparator 104 is connected to one input of the amplifier d of the latch circuit 114. The positive output of the comparator C_(N1) of the lower data comparator 104 is connected to one input of the amplifier b and one input of the amplifier c of the latch circuit 114, and the negative output is connected to the other input of the amplifier c and the other input of the amplifier d. The positive output of the comparator C_(n2) of the lower data comparator 104 is connected to one input of the amplifier a of the latch circuit 114, and the negative output is connected to the other input of the amplifier a and the other input of the amplifier b.

The positive output of the amplifier d of the latch circuit 114 is connected to the other input of the AND gate AD₁₃ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD₁₄ of the AND gate circuit 155; the positive output of the amplifier c is connected to the other input of the AND gate AD₁₄ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD₁₅ of the AND gate circuit 155; the positive output of the amplifier b is connected to the other input of the AND gate AD₁₅ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD₁₆ of the AND gate circuit 155; and the positive output of the amplifier a is connected to the other input of the AND gate AD₁₆ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD₂₁ of the AND gate circuit 155.

The positive output of the comparator C_(n1) of the lower data comparator 105 is connected to one input of the amplifier a of the latch circuit 115, and the negative output is connected to the other input of the amplifier a and one input of the amplifier b. The positive output of the comparator C_(N1) of the lower data comparator 105 is connected to the other input of the amplifier b and one input of the amplifier c of the latch circuit 115, and the negative output is connected to the other input of the amplifier c and one input of the amplifier d. The positive output of the comparator C_(n2) of the lower data comparator 105 is connected to the other input of the amplifier d of the latch circuit 115.

The positive output of the amplifier a of the latch circuit 115 is connected to one input of the AND gate AD₁₇ of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD₁₂ of the AND gate circuit 155; the positive output of the amplifier b is connected to one input of the AND gate A_(D18) of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD₁₇ of the AND gate circuit 155; the positive output of the amplifier c is connected to one input of the AND gate AD₁₉ of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD₁₈ of the AND gate circuit 155; and the positive output of the amplifier d is connected to one input of the AND gate AD₂₀ of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD₁₉ of the AND gate circuit 155.

The positive output of the comparator C_(n1) of the lower data comparator 106 is connected to one input of the amplifier d of the latch circuit 116. The positive output of the comparator C_(N1) of the lower data comparator 106 is connected to one input of the amplifier b and one input of the amplifier c of the latch circuit 116, and the negative output is connected to the other input of the amplifier c and the other input of the amplifier d. The positive output of the comparator C_(n2) of the lower data comparator 106 is connected to one input of the amplifier a of the latch circuit 116, and the negative output is connected to the other input of the amplifier a and the other input of the amplifier b.

The positive output of the amplifier d of the latch circuit 116 is connected to the other input of the AND gate AD₂₁ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD₂₂ of the AND gate circuit 155; the positive output of the amplifier c is connected to the other input of the AND gate AD₂₂ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD₂₃ of the AND gate circuit 155; the positive output of the amplifier b is connected to the other input of the AND gate AD₃₃ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD₂₄ of the AND gate circuit 155; and the positive output of the amplifier a is connected to the other input of the AND gate AD₁₄ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD₂₉ of the AND gate circuit 155.

The positive output of the comparator C_(n1) of the lower data comparator 107 is connected to one input of the amplifier a of the latch circuit 117, and the negative output is connected to the other input of the amplifier a and one input of the amplifier b. The positive output of the comparator C_(N1) of the lower data comparator 107 is connected to the other input of the amplifier b and one input of the amplifier c of the latch circuit 117, and the negative output is connected to the other input of the amplifier c and one input of the amplifier d. The positive output of the comparator C_(n2) of the lower data comparator 107 is connected to the other input of the amplifier d of the latch circuit 117.

The positive output of the amplifier a of the latch circuit 117 is connected to one input of the AND gate AD₂₅ of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD₂₀ of the AND gate circuit 155; the positive output of the amplifier b is connected to one input of the AND gate AD₂₆ of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD₂₅ of the AND gate circuit 155; the positive output of the amplifier c is connected to one input of the AND gate AD₂₇ of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD₂₆ of the AND gate circuit 155; and the positive output of the amplifier d is connected to one input of the AND gate AD₂₈ of the AND gate circuit 155, and the negative output is connected to one input of the OR gate OR_(D3) of the suppression circuit 122.

To the other input of the OR gate OR_(D3) of the suppression circuit 122, the outputs of the inverter 142 inverting the level of the outputs of the upper data side other output buffers B_(U1) and B_(U3) (AND gates A_(U1) and A_(U3) of the upper data comparators 151 and 153) are connected.

The output of the OR gate OR_(D3) is connected to the other input of the AND gate AD₂₇ of the AND gate circuit 130.

The positive output of the comparator C_(n1) of the lower data comparator 108 is connected to one input of the amplifier d of the latch circuit 118. The positive output of the comparator C_(N1) of the lower data comparator 108 is connected to one input of the amplifier b and one input of the amplifier c of the latch circuit 118, and the negative output is connected to the other input of the amplifier c and the other input of the amplifier d. The positive output of the comparator C_(n2) of the lower data comparator 108 is connected to one input of the amplifier a of the latch circuit 118, and the negative output is connected to the other input of the amplifier a and the other input of the amplifier b.

The positive output of the amplifier d of the latch circuit 118 is connected to the other input of the AND gate AD₂₉ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD₃₀ of the AND gate circuit 155; the positive output of the amplifier c is connected to the other input of the AND gate AD₃₀ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD_(D4) of the suppression circuit 122 and one input of the OR gate OR_(D4) ; the positive output of the amplifier b is connected to one input of the AND gate AD₃₁ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD_(D5) of the suppression circuit 122; and the positive output of the amplifier a is connected to one input of the AND gate AD₃₂ of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD_(D6) of the suppression circuit 122.

To the other inputs of the AND gates AD_(D4) to AD_(D6) and the OR gate OR_(D4) of the suppression circuit 122 are connected the outputs of the upper data side buffers B_(U1) and B_(U3) (the AND gates A_(U1) and A_(U3) of the upper data comparators 151 and 153).

The output of the OR gate OR_(D4) is connected to the input of the inverter I₂ of the AND gate circuit 155; the output of the AND gate AD_(D4) is connected to the other input of the AND gate AD₃₁ of the AND gate circuit 155; the output of the AND gate AD_(D5) is connected to the other input of the AND gate AD₃₂ of the AND gate circuit 155; and the output of the AND gate AD_(D6) is connected to the other input of the AND gate AD₂₈ of the AND gate circuit 155.

The outputs of the respective inverters I₁ and I₂ and the AND gates AD₁ to AD₃₂ of the AND gate circuit 155 are connected to the lower data encoder 140 via the buffers B_(D0) tO B_(D33), respectively.

A ring comparator is constituted by the above connection configuration. Where the ring comparator is constituted using the comparison circuit having an interpolation construction of FIG. 9, it is necessary to cut the left or right of the ring, and the suppression circuits 121 and 122 have this ring cutting function. The suppression circuit 121 is a circuit cutting the left of the ring, and the suppression circuit 122 is a circuit cutting the right of the ring.

Here, an explanation will be made of the fundamental operation of the suppression circuit of the third embodiment of the present invention using FIG. 11.

In FIG. 11, CN1 to CN8 are comparison circuits comparing the reference voltage divided by the reference resistance element R and the input signal V_(IN) as they are, and Cn denotes the comparison circuit using interpolation. FIG. 11 indicates a case where the left side of the ring is cut.

In this case, the lowest reference voltage is supplied to the comparison circuit CN1, and the highest reference voltage is supplied to the comparison circuit CN8.

For this reason, the outputs of the three interpolation comparison circuits of Cn_(a), Cn_(b), and Cn_(c) in FIG. 11 become unnecessary. So as not to input these outputs to the lower data encoder 140, the suppression circuit 121 acts so as to suppress the three outputs of the interpolation comparison circuits Cn_(a), Cn_(b), and Cn_(c).

This is the same also in the case where the right of the ring is cut.

The lower data encoder 140 is constituted by a data line LN₁₄₁ generating conversion code data D₂ to D₆, a selection line LN₁₄₂ generating a selection signal SEL₁ showing that one of the outputs of the AND gates AD₁, AD₂, AD₅ to AD₈, AD₁₃, and AD₁₄ of the AND gate circuit 155 becomes "1"; a selection line LN₁₄₃ generating a selection signal SEL₂ indicating that one of the outputs of the inverter I₁, AND gates AD₂, AD₃, AD₄, AD₉ to AD₁₂, AD₁₇ to AD₂₀, AD₂₅ to AD₂₈, AD₃₁, and AD₃₂ of the AND gate circuit 155 becomes "1"; and a selection line LN₁₄₄ generating a selection signal SEL₃ indicating that one of the outputs of the AND gates AD₁₅, AD₁₆, AD₂₁ to AD₂₄, AD₂₉, and AD₃₀ , and the inverter I₂ of the AND gate circuit 155 becomes "1".

FIG. 12 shows the correspondence between the output conversion code data D₂ to D₆ and the selection line data LN₁₄₂ to LN₁₄₄ which is the result of encoding of the lower data encoder 140 when the outputs of the inverters I₁ and I₂ and AD₁ to AD₃₂ of the lower data side AND gate circuit 155 are "1".

Next, the operation by the above-described structure will be explained.

For example, when the sampling voltage V_(S) of the sampled analog signal is represented as V_(RB) <V_(S) <V₃ (=e₁₂), the outputs of the comparators CU₁ to CU₃ of the upper data comparators 151 to 153 become "L", and the digital signals of "0" are output from the AND gates AU₁ to AU₃, respectively.

As a result, the digital signal such as [000] is input via the buffers B_(U1) to B_(U3) to the upper data encoder 130. The outputs of the AND gates AU₁ and AU₃ pass through the buffers B_(U1) to B_(U3), and then are input to the suppression circuits 121 and 122 directly or after an inversion of the level at the inverter 80.

At the upper data encoder 130, the upper significant data of [000] is issued to the three columns of encoder lines [LN₃₁ ] to [LN₃₃ ] generating the predetermined data by a so-called wired-OR circuit and is output to the selection gate 141.

Also, at this time, only the outputs of the AND gates AD_(U4) and AD_(U5) among the upper data side AND gates AD_(U1) to AD_(U5) become "H", and the control signals x₄ and x₅ of "1" are output from the AND gates AD_(U4) and AD_(U5).

Also, if the sampling voltage V_(S) is represented as V₃ <V_(S) <V₂ (=e₈), the outputs of the comparators CU₁ and CU₂ of the upper data comparators 151 and 151 become "L", and the output of the comparator CU₃ of the upper data comparator 153 becomes "H", and the digital signal is output, i.e., "0" is output from the AND gates AU₁ and AU₂ of the upper data comparators 151 and 152, and "1" is output from the AND gate AU₃ of the upper data comparator 153, respectively.

As a result, the digital signal such as [001] is input via the buffers B_(U1) to B_(U3) to the upper data encoder 155, and the outputs of the AND gates AU₁ and AU₃ pass through the buffers B_(U1) and B_(U3), and then are input to the suppression circuits 121 and 122 directly or after being inverted in their levels at the inverter 142.

At the upper data encoder 130, the upper significant data of [001] is generated to the encoder lines [LN₃₁ ] to [LN₃₃ ] and is output to the selection gate 141.

Also, at this time, only the outputs of the AND gates AD_(U3) and AD_(U4) among the upper data side AND gates AD_(U1) to AD_(U5) become "H", and the control signals x₁₃ and x₁₄ of "1" are output from the AND gates AD_(U3) and AD_(U4).

Also, if the sampling voltage V_(S) is represented as V₃₂ <V_(S) <V₃₁, the outputs of the comparators CU₂ and CU₃ of the upper data comparators 152 and 153 become "H", the output of the comparator CU₁ of the upper data comparator 151 becomes "L", and the digital signal is output, i.e., "1" is output from the AND gate AU₂ of the upper data comparator 152, and "0" is output from the AND gates AU₁ and AU₃ of the upper data comparators 151 and 153, respectively.

As a result, a digital signal such as [010] is input via the buffers B_(U1) to B_(U3) to the upper data encoder 155, and the outputs of the AND gates AU₁ and AU₃ pass through the buffers B_(U1) and B_(U3) and then are input to the suppression circuits 121 and 122 directly or after being inverted in their levels at the inverter 142.

At the upper data encoder 130, the upper significant data of [011] is generated to the encoder lines [LN₃₁ ] to [LN₃₃ ] and is output to the selection gate 141.

Also, at this time, only the outputs of the AND gates AD_(U2) and AD_(U3) among the upper data side AND gates AD_(U1) to AD_(U5) become "H", and the control signals x₁₂ and x₁₃ of "1" are output from the AND gates AD_(U2) and AD_(U3).

Also, if the sampling voltage V_(S) is represented as V₃₁ <V_(S) <V_(RT), the outputs of the comparators CU₁ to CU₃ of the upper data comparators 151 to 153 become "H", and a digital signal is output, i.e., "1" is output from the AND gate AU₂ of the upper data comparator 151, and "0" is output from the AND gates AU₂ and AU₃ of the upper data comparators 152 and 153, respectively.

As a result, a digital signal such as [100] is input via the buffers B_(U1) to B_(U3) to the upper data encoder 155, and the outputs of the AND gates AU₁ and AU₃ pass through the buffers B_(U1) and B_(U3) and then are input to the suppression circuits 121 and 122 directly or after being inverted in their levels at the inverter 142.

At the upper data encoder 130, the upper significant data of [110] is generated to the encoder lines [LN₃₁ ] to [LN₃₃ ] and is output to the selection gate 70.

Also, at this time, only the outputs of the AND gates AD_(U1) and AD_(U2) among the upper data side AND gates AD_(U1) to AD_(U5) become "H", and the control signals x₁₁ and x₁₂ of "1" are output from the AND gates AD_(U1) and AD_(U2).

In parallel with this, the transistors Q₁₀₃ of the respective switching blocks of the matrix circuit 100 connected to the control lines (x₁₁, x₁₂, x₁₃, x₁₄ and x₁₅) at which the digital output signal among the respective upper data side AND gates AD_(U)(1, 2, 3, 4, 5) has become "1" are controlled to turn ON in units of two rows, and further a fine digitization of the quantization level is executed.

For example, when the outputs of the output control signals x₁₄ and x₁₃ of the AND gates AD_(U4) and AD_(U3) become the "1" level (at this time, only the output of the AND gate A_(U3) is the "1" level), respective transistors Q₁₀₃ of the switching blocks S_(C41), S_(C43), S_(C45), and S_(C47) at the second row from the bottom in the diagram, and the switching blocks S_(C32), S_(C34), S_(C36), and S_(C38) at the third row adjoining them become ON, so that the reference voltages e₇ to e₁₅ divided by the reference resistors R₇ to R₁₆ and the sampling voltage V_(S) are differentially amplified at the respective switching blocks S_(C41), S_(C43), S_(C45), and S_(C47), and S_(C32), S_(C34), S_(C36), and S_(C38), and the differential output is input to the 2-input ends of the comparators C_(N1), C_(n1), and C_(n2) of the lower data comparators 101 to 108.

Similarly, when the outputs of the output control signals x₁₃ and x₁₂ of the AND gates AD_(U3) and AD_(U2) become the "1" level (at this time, only the output of the AND gate A_(U2) is the "1" level), the switching blocks S_(C32), S_(C34), S_(C36), and S_(C38) at the third row, and the switching blocks S_(C21), S_(C23), S_(C25), and S_(C27) at the second row adjoining them are activated, so that the differential amplification operation is performed, and the differential output is input to the 2-input ends of the comparators C_(N1), C_(n1), and C_(n2) of the lower data comparators 101 to 108.

For example, when the output of the AND gate AU₂ is at "1" level, the lower data conversion code is detected by the switching blocks S_(C21), S_(C23), S_(C32), and S_(C34), and the redundant bit of the lower data conversion code is detected by the switching blocks S_(C25), S_(C27), S_(C36), and S_(C38).

The outputs of the comparators C_(n1) and C_(n2) of the respective lower data comparators 101 to 108 having the gain of n₁ (or n₂) are connected to the comparators C_(n1) and C_(n2) of the lower data comparators corresponding to the adjoining columns or corresponding to every other column, whereby the ring comparator is constituted, and the differential outputs between the sampled voltage V_(S) obtained at the activated switching block and the reference voltage divided by the reference resistance element are compared between the two comparators C_(N1) and C_(n1) of the connected two lower data comparators or by the comparison circuit having an interpolation construction constituted by C_(n1) and C_(n2). As a result, an interpolation output is obtained, which is input to the respective latch circuits 111 to 118.

The output of the latch circuit 118 is input to the inverters I₁ and I₂ and the AND gates A_(D1) to A_(D32) of the AND gate circuit 130 via the suppression circuits 121 and 122 or directly, whereby a digital signal in accordance with the result of comparison will be output to the lower data encoder 140.

Note that, at this time, in the suppression circuits 121 and 122, based on the output signal of the upper data comparators 151 and 153, cutting is carried out on the left side or right side of the ring comparator and, at the same time, the unnecessary input of the output of the interpolation circuit to the lower data encoder 140 is suppressed.

At the lower data encoder 140, by the wired-OR circuit, as shown in FIG. 12, the output conversion codes D₂ to D₆ are set at the line LN₁₄₁ in accordance with the output level of the inverters I₁ and I₂ and the AND gates AD₁ to AD₃₂ of the AND gate circuit 155 and output, and at the same time, one line among the selection lines LN₁₄₂ to LN₁₄₄ is set at "1", which is input as the selection signals SEL₁ to SEL₃ to the AND gates A₁ to A₃ of the selection gate 70, respectively.

At this time, where for example the output of the AND gate AD₁ of the AND gate circuit 155 is at the "1" level, the conversion codes D₂ to D₆ are set at [00110] and output, the selection signal SEL₁ is input to the AND gate A₁ of the selection gate 70 as the "1" level, and the selection signals SEL₂ and SEL₃ are input to the AND gates A₂ and A₃ of the selection gate as the "0" level.

At the selection gate 141, along with the fact that only the selection signal SEL₁ is input as the "1" level, only the AND gate A₁ is activated.

To the AND gate A₁, the upper significant data generated in the line LN₃₁ of the upper data encoder 130 has been supplied.

Accordingly, the upper significant data generated in the line LN₃₁ is selected at the selection gate 141, and as a result, it is output as the upper data conversion code D₁ via the OR gate OR₁.

As explained above, according to the present embodiment, the lower data comparators 101 to 108 corresponding to respective columns of the switching block are constituted by the comparator C_(N1) having a gain of N and comparators C_(n1) and C_(n2) having a gain of n₁ (or n₂) and, at the same time, a ring comparator is constituted by connecting the outputs of the comparators C_(n1) and C_(n2) to the comparators C_(n1) and C_(n2) of the lower data comparators corresponding to the adjoining columns or corresponding to every other column, and constituted so that the differential outputs between the sampled voltage V_(S) obtained at the activated switching block and the reference voltage divided by the reference resistance element are compared between the two comparators C_(N1) and C_(n1) of the connected two lower data comparators or by the comparison circuit having an interpolation construction constituted by C_(n1) and C_(n2), whereby an interpolation output is obtained and, provision is made of suppression circuits 121 and 122 which act as the left side or right side of the ring comparator in accordance with the outputs of the upper data comparators 151 and 153 and, at the same time, suppress the unnecessary input of the output of the interpolation circuit to the lower data encoder 140. Therefore, a great improvement of the resolution can be achieved, and an A/D converter circuit having a high precision can be realized.

Also, the restrictions with respect to the emitter size of the reference resistance element and transistor are eased, and as a result, the elements can be made smaller, and thus there is an advantage that a reduction of the surface area of the chip can be achieved and so on.

Also, in the above-mentioned embodiment, the structure in which the other output pin buffers B_(U1) to B_(U3) and B_(D0) to B_(D33) are arranged on the input side of the upper data encoder 30 and the lower data encoder 140 was shown, but these other output pin buffers B_(U1) to B_(U3) and B_(D0) to B_(D33) are provided so as to reliably drive the upper data encoder 130 and the lower data encoder 140. It is necessary to provide the same according to a certain capacitance of the upper data encoder 130 and the lower data encoder 140 acting as a so-called load.

As explained above, according to the present invention, a great improvement of the resolution can be achieved, and an A/D converter circuit having a high precision can be realized.

Also, the restrictions with respect to the emitter size of the reference resistance element and transistor are eased, and as a result, the elements can be made smaller, and thus there is an advantage that a reduction of the surface area of the chip can be achieved and so on.

An explanation will now be made of a fourth embodiment of the present invention.

FIG. 13 is a structural view showing a fourth embodiment of an A/D converter circuit according to the present invention.

R₇₁ to R₈₆ denote reference resistance elements; CU₁₁ to CU₁₃ denote upper data comparators; AU₁₅ to AU₁₇ denote upper data side AND gates; E_(U1) denotes an upper data encoder; S_(d1) to S_(d12) denote switching blocks; EOD₁ to EOD₃ denote even/odd determination circuits; B_(D1) to B_(D3) denote complementary output buffers; AD₅₁ to AD₅₃ denote lower data side AND gates; E_(D1), a lower data encoder; RV₁, an inverted gate; V_(IN), an input analog signal; and V_(RT) and V_(RB) denote reference voltages set with a predetermined differential therebetween; respectively.

The reference resistance elements R₇₁ to R₈₆ are connected in series between the terminals of the reference voltages V_(RT) to V_(RB) (0 to -2 V) and generate the reference voltages V₁ to V₁₅ obtained by dividing the reference voltage between the adjoining resistance elements, respectively.

The upper data comparator CU₁₅ is connected to the input line of the analog signal V_(IN) which is to be converted at its one input terminal, is connected to the middle point of connection of the resistance elements R₇₄ and R₇₅ generated by the reference voltage V₄₄ of the rough quantization level divided by the reference resistance elements R₇₁ to R₈₆ at its other input terminal, and is connected to one input terminal of the 2-input AND gate AU₁₅ at its positive output terminal.

This upper data comparator CU₁₅ compares the input analog signal V_(IN) with the reference voltage V₄₄ and outputs the signal indicating the result of that comparison at a high level ("1") when the level of the analog signal V_(IN) is higher than the reference voltage V₄₄, while at a low level ("0") when the level of the analog signal V_(In) is lower than the reference voltage V₄₄, to the AND gate AU₁₁ from its positive output terminal.

The upper data comparator CU₁₆ is connected to the input line of the analog signal V_(IN) which is to be converted at its one input terminal, is connected to the middle point of connection of the resistance elements and R₇₉ generated by the reference voltage V₄₈ of the rough quantization level divided by the reference resistance elements R₇₁ to R₈₆ at its other input terminal, is connected to one input terminal of the 2-input AND gate AU₁₆ at its positive output terminal, and is connected to the other input terminal of the 2-input AND gate AU₁₅ at its negative output terminal.

This upper data comparator CU₁₆ compares the input analog signal V_(IN) with the reference voltage V₄₈, outputs the signal indicating the result of that comparison at a high level when the level of the analog signal V_(IN) is higher than the reference voltage V₄₈, while at a low level when the level of the analog signal V_(IN) is lower than the reference voltage V₄₈, to the AND gate AU₁₆ from its positive output terminal and outputs the signal obtained by inverting the level of the positive output to the other input terminal of the AND gate AU₁₅ from its negative output terminal.

The upper data comparator CU₁₇ is connected to the input line of the analog signal V_(IN) which is to be converted at its one input terminal, is connected to the middle point of connection of the resistance elements R₈₂ and R₈₃ generated by the reference voltage V₁₂ of the rough quantization level divided by the reference resistance elements R₇₁ to R₈₆ at its other input terminal, is connected to the two input terminals of the 2-input AND gate AU₁₇ at its positive output terminal, and is connected to the other input terminal of the 2-input AND gate AU₁₆ at its negative output terminal.

This upper data comparator CU₁₇ compares the input analog signal V_(IN) with the reference voltage V₅₂, outputs the signal indicating the result of that comparison at a high level when the level of the analog signal V_(IN) is higher than the reference voltage V₅₂, while at a low level when the level of the analog signal V_(IN) is lower than the reference voltage V₅₂, to the AND gate AU₁₇ from its positive output terminal, and outputs the signal obtained by inverting the level of the positive output to the other input terminal of the AND gate AU₁₆ from its negative output terminal.

The AND gate AU₁₅ obtains the logical product between the positive output of the upper data comparator CU₁₅ and the negative output of the upper data comparator CU₁₆ and outputs the result of the same to the upper data encoder E_(U1).

The AND gate AU₁₆ obtains a logical product between the positive output of the upper data comparator CU₁₆ and the negative output of the upper data comparator CU₁₇ and outputs the result of the same to the upper data encoder E_(U1).

The AND gate AU₁₇ obtains a logical product for the positive output of the upper data comparator CU₁₇ as a 2-input and outputs the result of the same to the upper data encoder E_(U1).

The upper data encoder E_(U1) encodes the output signals of the respective AND gates AU₁₅ to AU₁₇ in accordance with the output levels of the same, converts the same to a digital code of 2 bits, and outputs the result as the conversion codes D₀ and D₁ of the upper significant 2 bits.

Concretely, where the output levels of the AND gates AU₁₅ to AU₁₇ are all "0", the conversion codes D₀ and D₁ are set to [0,0] and output; where the output level of the AND gate AU₁₅ is "1", they are set to [0,1] and output; where the output level of the AND gate AU₁₆ is "1", they are set to [1,0] and output; and where the output level of the AND gate AU₁₇ is "1", they are set to [1,1] and output.

The switching blocks S_(d1) to S_(d2) are arranged in the form of a matrix comprising four rows and three columns and constituted by for example differential type amplifiers, which compare one reference voltage among the reference voltages V₄₁ to V₅₅ (note, V₄₄, V₄₈, and V₅₂ are excluded) divided by the reference resistance elements R₇₁ to R₈₆ with the input analog signal V_(IN), and in accordance with the magnitude of the input analog signal V_(IN) with respect to the reference voltage. Concretely, in the case of (V_(IN) >reference voltage V), they output S₁ to S₁₂ of "1", and in the case of (level V_(IN) ≦reference voltage V), S₁ to S₁₂ of the "0" level to the corresponding even/odd determination circuits EOD₁ to EOD₃ arranged in accordance with the columns.

Explaining this in further detail, the switching blocks S_(d1), S_(d6), S_(d7), and S_(d12) arranged in the first column (left side in the figure) compare the reference voltages V₄₁, V₄₇, V₄₉, and V₅₅ with the analog signal V_(IN), respectively, and output the results of this as the signals S₉₁, S₉₆, S₉₇, and S₁₀₂ to the even/odd determination circuit EOD₁.

The switching blocks S_(d2), S_(d5), S_(d8), and S_(d11) arranged in the second column compare the reference voltages V₄₂, V₄₆, V₅₀, and V₅₄ with the analog signal V_(IN), respectively, and output the results of this as the signals S₉₂, S₉₅, S₉₈, and S₁₀₁ to the even/odd determination circuit EOD₂.

The switching blocks S_(d3), S_(d4), S_(d9) and S_(d10) arranged in the third column compare the reference voltages V₄₃, V₄₅, V₅₁, and V₅₃ with the analog signal V_(IN), respectively, and output the results of this as the signals S₉₃, S₉₄, S₉₉, and S₁₀₀ to the even/odd determination circuit EOD₃.

The even/odd determination circuit EOD₁ determines whether or not there are an even number of the signals S₉₁, S₉₆, S₉₇, and S₁₀₂ which are output from the switching blocks S_(d1), S_(d6), S_(d7), and S_(d12) and simultaneously input which have an input level of "1". It outputs the signal S_(EO1) to the buffer B_(D1) with the "0" level where it determines that the number is even, while with the "1" level where it determines that the number is not even, that is, an odd number.

The even/odd determination circuit EOD₂ determines whether or not there are even number of signals S₉₂, S₉₅, S₉₈, and S₁₀₁ which are output from the switching blocks S_(d2), S_(d5), S_(d8), and S_(d11) and simultaneously input which have an input level of "1". It outputs the signal S_(EO2) to the buffer B_(U2) with the "0" level where it determines that the number is even, while with the "1" level where it determines that the number is odd.

The even/odd determination circuit EOD₃ determines whether or not there are an even number of the signals S₉₃, S₉₄, S₉₉, and S₁₀₀ which are output from the switching blocks S_(d3), S_(d4), S_(d9), and S_(d10) and simultaneously input which have an input level of "1". It outputs the signal S_(EO3) to the buffer B_(D3) with the "0" level where it determines that the number is even, while with the "1" level where it determines that the number is odd.

FIG. 14 is a view showing an example of the circuit structure of the switching block and even/odd determination circuit for each column, in which FIG. 14A shows an example of the circuit structure of the switching blocks S_(d1), S_(d6), S_(d7), and S_(d12) and the even/odd determining circuit EOD₁ at the first column; FIG. 14B shows an example of the circuit structure of the switching blocks S_(d2), S_(d5), S_(d8), and S_(d11) and the even/odd determining circuit EOD₂ at the second column; and FIG. 14C shows an example of the circuit structure of the switching blocks S_(d3), S_(d4), S_(d9), and S_(d10) and the even/odd determining circuit EOD₃ at the third column; respectively.

These circuits have the same fundamental structure and function in each column except the input reference voltage differs, and therefore an explanation will be made here of the structure of the example of FIG. 14A.

In FIG. 14A, V_(CC) denotes a power source voltage; LR₁ and LR₂ denote load resistance elements of the resistance value R; Q₁₂₁ to Q₁₂₈ denote npn-type transistors; and I_(C11) to I_(C14) denote constant current sources supplying the current I; respectively.

The constant current source I_(C11) is connected to the emitter of the transistor Q₁₂₁ and the emitter of the transistor Q₁₂₂, so that the switching block S_(d1) comprising a differential amplifier is constituted; the constant current source I_(C12) is connected to the emitter of the transistor Q₁₂₃ and the emitter of the transistor Q₁₂₄, so that the switching block S_(d6) comprising a differential amplifier is constituted; a constant current source I_(C13) is connected to the emitter of the transistor Q₁₂₅ and the emitter of the transistor Q₁₂₆, so that the switching block S_(d7) comprising a differential amplifier is constituted; and the constant current source I_(C14) is connected to the emitter of the transistor Q₁₂₇ and the emitter of the transistor Q₁₂₈, so that the switching block S_(d12) comprising a differential amplifier is constituted.

Then, the system is constituted so that an analog signal V_(IN) is input to the respective bases of the transistors Q₁₂₁, Q₁₂₃, Q₁₂₅, and Q₁₂₇ ; the reference voltage V₄₁ is input to the base of the transistor Q₁₂₂ ; the reference voltage V₄₇ is input to the base of the transistor Q₁₂₄ ; the reference voltage V₄₉ is input to the base of the transistor Q₁₂₆ ; and the reference voltage V₅₅ is input to the base of the transistor Q₁₂₈ ; respectively.

The even/odd determining circuit EOD₁ is constituted by the combination of connection of the respective collectors of the respective transistors Q₁₂₁ to Q₁₂₈ with respect to the load resistance elements LR₁ and LR₂.

Namely, the collectors of the transistors Q₁₂₁, Q₁₂₄, Q₁₂₅, and Q₁₂₈ are connected to the power source voltage V_(CC) via the load resistance element LR₂ ; the collectors of the transistors Q₁₂₂, Q₁₂₃, Q₁₂₆, and Q₁₂₇ are connected to the power source voltage V_(CC) via the load resistance element LR₁ ; and the output terminal of the signal S_(EO1) is constituted by the connection point between the collector of the transistor Q₁₂₇ and the load resistance element LR₁.

Explaining an example of the fundamental operation of the structure of FIG. 14A, for example in the case where V_(IN) <V₄₁, the reference voltages V₄₁, V₄₇, V₄₉, and V₅₅ are larger than the input analog signal V_(IN) in all of the switching blocks S_(d1), S_(d6), S_(d7), and S_(d12), and therefore the transistors Q₁₂₂, Q₁₂₄, Q₁₂₆, and Q₁₂₈ become ON. As a result, a current such as 2I flows through the load resistance elements LR₁ and LR₂, respectively.

Accordingly, the level of the output signal S_(EO1) becomes (V_(CC) -2I·R).

Also, in the case where V₄₁ <V_(IN) <V₄₇, the transistors Q₁₂₁, Q₁₂₄, Q₁₂₆, and Q₁₂₈ become ON. As a result, a current such as I flows through the load resistance element LR₁, and a current such as 3I flows through the load resistance element LR₂.

Accordingly, the level of the output signal S_(EO1) becomes (V_(CC) -I·R).

Namely, when the differential pair (switching block) of (analog signal V_(IN) >reference voltage V) is even, the level of the output signal S_(EO1) becomes (V_(CC) -2I·R) at the low level, while becomes (V_(CC) -I·R) at the high level when it is the odd number.

The complementary output buffer B_(D1) is connected to the output terminal of the even/odd determining circuit EOD₁ at its input terminal and is connected to one input terminal of the AND gate AD₅₁ at its positive output terminal.

This buffer B_(D1) performs the predetermined level adjustment of the even/odd determining circuit EOD₁ with respect to the output signal S_(EO1) and outputs the result to one input terminal of the AND gate AD₅₁ from its positive output terminal.

The complementary output buffer B_(D2) is connected to the output terminal of the even/odd determining circuit EOD₂ at its input terminal, connected to one input terminal of the AND gate AD₅₂ at its positive output terminal, and connected to the other input terminal of the AND gate AD₅₁ at its negative output terminal.

This buffer B_(D2) performs the predetermined level adjustment of the even/odd determining circuit EOD₂ with respect to the output signal S_(EO2) and outputs the result to one input terminal of the AND gate AD₅₂ from its positive output terminal; while outputs the inverted input level to the other input terminal of the AND gate AD₅₁ from its negative output terminal.

The complementary output buffer B_(D3) is connected to the output terminal of the even/odd determining circuit EOD₃ at its input terminal, connected to the two input terminals of the AND gate AD₅₃ at its positive output terminal, and connected to the other input terminal of the AND gate AD₅₂ at its negative output terminal.

This buffer B_(D3) performs the predetermined level adjustment of the even/odd determining circuit EOD₃ with respect to the output signal S_(EO3) and outputs the result to the two input terminals of the AND gate AD₅₃ from its positive output terminal; while outputs the inverted input level to the other input terminal of the AND gate AD₅₂ from its negative output terminal.

The AND gate AD₅₁ obtains the logical product between the positive output of the buffer BD₁ and the negative output of the buffer BD₄₅ and outputs the result thereof to the lower data encoder E_(D1).

The AND gate AD₅₂ obtains the logical product between the positive output of the buffer BD₄₅ and the negative output of the buffer BD₄₆ and outputs the result thereof to the lower data encoder E_(D1).

The AND gate AD₅₃ obtains the logical product between two inputs of the positive output of the buffer BD₄₆ and outputs the result thereof to the lower data encoder E_(D1).

The lower data encoder E_(D1) encodes the output signals of the respective AND gates AD₅₁ to AD₅₃ in accordance with the output levels of the same, converts the same to the 2 bits of a digital code, and outputs the same as preceding output codes BD₄₅ and BD₄₆ of the conversion codes D₂ and D₃ of the lower significant 2 bits to the inverted gate RV₁.

Concretely, it sets the preceding output codes BD₄₅ and BD₄₆ to [0,0] and outputs the same where the output levels of the AND gates AD₅₁ to AD₅₃ are all "0"; sets the same to [0,1] where the output level of the AND gate AD₅₁ is "1" and outputs the result; sets the same to [1,0] where the output level of the AND gate AD₅₂ is "1" and outputs the result; and sets the same to [1,1] where the output level of the AND gate AD₅₃ is "1" and outputs the result.

The inverted gate RV₁ is constituted by for example parallel-arranged exclusive-OR gates EXO₁ and EXO₂, obtains the exclusive-OR between the preceding output codes BD₄₅ and BD₄₆ output from the lower data encoder E_(D1) and the output conversion code D₁ of the upper data encoder E_(D1), and outputs the same as the conversion codes D₂ and D₃ of the lower significant 2 bits.

Concretely, it obtains the exclusive-OR between the preceding output code BD₄₅ and the upper data conversion code D₁ at the exclusive-OR gate EXO₁, outputs the result thereof as the lower data conversion code D₂, obtains the exclusive-OR between the preceding output code BD₄₆ and the upper data conversion code D₁ at the exclusive-OR gate EXO₂, and outputs the result thereof as the lower data conversion code D₃.

Next, an explanation will be made of the operation by the above-described structure in sequence dividing the same into the upper data conversion and the lower data conversion and referring to FIG. 15 and FIG. 16.

Note that, FIG. 15 shows the correspondence between the output levels of the upper data comparators CU₁₅ to CU₁₇, output levels of the AND gates AU₁₅ to AU₁₇, and the output levels of the conversion codes D₀ and D₁ in accordance with the magnitude of the input voltage (analog signal) level at the time of upper data conversion with respect to the reference voltages V₄ to V₁₂.

Also, FIG. 16 shows the correspondence between the levels of the output signals S₉₁ to S₁₀₂ of the switching blocks S_(d1) to S_(d2), the levels of the output signals S_(EO1) to S_(EO3) of the even/odd determining circuit EOD₁ to EOD₃, the output levels of the AND gates AD₅₁ to AD₅₃, and the output levels of the conversion codes D₂ and D₃, in accordance with the magnitude of the input voltage (analog signal) level at the time of lower data conversion with respect to the reference voltages V₁ to V₄.

First, the upper data conversion operation will be explained using FIG. 15.

The reference voltages V₄, V₈, and V₁₂ of the rough quantization level divided by the reference resistance elements R₇₁ to R₈₆ and the input analog signal V_(IN) are compared by the upper data comparators CU₁₅ to CU₁₇, respectively.

As a result of this comparison, if for example V_(IN) < V₄₄, as shown in FIG. 15, the outputs of the upper data comparators CU₁₅, CU₁₆, and CU₁₇ become all the "0" level.

By this, also the output levels of the AND gates AU₁₅ to AU₁₇ become all "0".

As a result, [00] is output as the upper significant 2 bits of the conversion codes D₀ and D₁ from the upper data encoder E_(U1).

As a result of comparison, if for example V₄₄ <V_(IN) <V₄₈, the output of the upper data comparator CU₁₅ becomes the "1" level, and the outputs of the upper data comparators CU₁₆ and CU₁₇ become the "0" level.

By this, among the output levels of the AND gates AU₁₅ to AU₁₇, only the output of the AND gate AU₁₅ becomes "1", and the outputs of the other AND gates AU₁₆ and AU₁₇ become "0".

As a result, [01] is output as the upper significant 2 bits of the conversion codes D₀ and D₁ from the upper data encoder E_(U1).

As a result of comparison, if for example V₄₈ <V_(IN) <V₅₂, the outputs of the upper data comparators CU₁₅ and CU₁₆ become the "1" level, and the output of the upper data comparator CU₁₇ becomes the "0" level.

By this, among the output levels of the AND gates AU₁₅ to AU₁₇, only the output of the AND gate AU₁₅ becomes "1", and the outputs of the other AND gates AU₁₅ and AU₁₇ become "0".

As a result, [10] is output as the upper significant 2 bits of the conversion codes D₀ and D₁ from the upper data encoder E_(U1).

Further, as a result of comparison, if for example V₅₂ <V_(IN), the outputs of the upper data comparators CU₁₅, CU₁₆ and CU₁₇ become all the "1" level.

By this, among the output levels of the AND gates AU₁₅ to AU₁₇, only the output of the AND gate AU₁₇ becomes "1", and the outputs of the other AND gates AU₁₅ and AU₁₆ become "0".

As a result, [11] is output as the upper significant 2 bits of conversion codes D_(O) and D₁ from the upper data encoder E_(U1).

Next, an explanation will be made of the lower data conversion operation using FIG. 16.

At the time of the conversion operation, all switching blocks S_(d1) to S_(d2) are in the ON state, the input analog signal V_(IN) is compared with the corresponding reference voltages V₄₁ to V₄₃, V₄₅ to V₄₇, V₄₉ to V₅₁ and V₅₃ to V₅₅ of the fine quantization level divided by the reference resistance elements R₇₁ to R₈₆ in the respective switching blocks S_(d1) to S_(d2), respectively.

In the respective switching blocks S_(d1) to S_(d12), as a result of comparison, if V_(IN) >reference voltage V, the output signals S₉₁ to S₁₀₂ are output as the "1" level, while if V_(IN) ≦reference voltage V, the output signals V₉₁ to S₁₀₂ are output as the "0" level.

Accordingly, if for example V_(IN) <V₄₁, the signals S₉₁ to S₁₀₂ of the "0" level are output from all switching blocks S_(d1) to S_(d2). Namely, the number of signals of the "1" level of each column is zero.

Accordingly, the signals S_(EO1) to S_(EO3) are output as the "0" level from all even/odd determining circuits EOD₁ to EOD₃, and also the output levels of the lower data side AND gates AD₅₁ to AD₅₃ become all "0".

As a result, [00] is output as the preceding output codes BD₄₂ and BD₄₃ of the lower significant 2 bits from the lower data encoder. At this time, since also the conversion code D₁ by the upper data encoder E_(U1) is [0], the preceding output codes BD₄₂ and BD₄₃ are not subjected to the inversion function at the inverted gate RV₁ and are output as the lower data conversion codes D₂ and D₃ while holding their level [00] as they are.

Also, if V₁ <V_(IN) <V₂, only the output signal S₁ of the switching block S_(d1) is output as the "1" level, and the output signals S₉₂ to S₁₀₂ of the remaining switching blocks S_(d2) to S_(d12) are output as the "0" level. Namely, the number of signals of the "1" level in the left first column is (1), and the number of the signals of the "1" level in the second and third columns is zero.

Accordingly, the signal S_(EO1) is output as the "1" level from the even/odd determining circuit EOD₁, and the signals S_(EO2) and S_(EO3) are output as the "0" level from the even/odd determining circuits EOD₂ and EOD₃.

By this, among the output levels of the AND gates AD₅₁ to AD₅₃, only the output of the AND gate AD₅₁ becomes "1", and the outputs of the other AND gates AD₅₂ and AD₅₃ become "0".

As a result, [01] is output as the preceding output codes BD₄₂ and BD₄₃ of the lower significant 2 bits from the lower data encoder E_(D1). At this time, since also the conversion code D₁ by the upper data encoder E_(U1) is [0], the preceding output codes BD₄₂ and BD₄₃ are not subjected to the inversion function at the inverted gate RV₄₁ and are output as the lower data conversion codes D₂ and D₃ while holding their level [01] as they are.

Also, if V₄₂ <V_(IN) <V₄₃, only the output signals S₉₁ and S₉₂ of the switching blocks S_(d1) and S_(d2) are output as the "1" level, and the output signals S₉₃ to S₁₀₂ of the remaining switching blocks S_(d3) to S_(d12) are output as the "0" level. Namely, the number of signals of the "1" level in the first column and second column is one, and the number of the signals of the "1" level in the third column is zero.

Accordingly, the signals S_(EO1) and S_(EO2) are output as the "1" level from the even/odd determining circuits EOD₁ and EOD₂, and the signal S_(EO3) is output as the "0" level from the even/odd determining circuit EOD₃.

By this, among the output levels of the AND gates AD₅₁ to AD₅₃, only the output of the AND gate AD₅₂ becomes "1", and the outputs of the other AND gates AU₁₅ and AU₁₇ become "0".

As a result, [10] is output as the preceding output codes BD₄₂ and BD₄₃ of the lower significant 2 bits from the lower data encoder E_(D1). At this time, since also the conversion code D₁ by the upper data encoder E_(U1) is [0], the preceding output codes BD₄₂ and BD₄₃ are not subjected to the inversion function at the inverted gate RV₁ and are output as the lower data conversion codes D₂ and D₃ while holding their level [20] as they are.

Further, if V₄₃ <V_(IN) <V₄₄, only the output signals S₉₁, S₉₂, and S₉₃ of the switching blocks S_(d1), S_(d2), and S_(d3) are output as the "1" level, and the output signals S₉₄ to S₁₀₂ of the remaining switching blocks S_(d4) to S_(d12) are output as the "0" level. Namely, the number of signals of the "1" level of all columns of the first column, second column, and third column is one.

Accordingly, the signals S_(EO1) to S_(EO3) are output as the "1" level from the even/odd determining circuits EOD₁ to EOD₃.

By this, among the output levels of the AND gates AD₅₁ to AD₅₃, only the output of the AND gate AD₅₃ becomes "1", and the outputs of the other AND gates AU₁₅ and AU₁₆ become "0".

As a result, [11] is output as the preceding output codes BD₄₂ and BD₄₃ of the lower significant 2 bits from the lower data encoder E_(D1). At this time, since also the conversion code D₁ by the upper data encoder E_(U1) is [0], the preceding output codes BD₄₂ and BD₄₃ are not subject to the inversion function at the inverted gate RV₁ and are output as the lower data conversion codes D₂ and D₃ while holding their level [11] as they are.

In above way, the lower data conversion code is obtained. In the case where the reference voltage V₄ <V_(IN) as well, the conversion operation of lower significant data is similarly carried out.

Note, in the case where V₄₄ <V_(IN) <V₄₈ and V₅₂ <V_(IN), due to the restrictions of the circuit structure etc., the direction of application of the reference voltage from the second row to the fourth row of the switching block array from the bottom in FIG. 13 has become reverse to that at the first row and the third row, and therefore the levels of the preceding output codes BD₄₅ and B₄₆ are inverted, and thus the level is returned to the normal level at the inverted gate RV₁ and output as the lower data conversion codes D₂ and D₃.

As explained above, according to the present embodiment, by simultaneously actuating all of the switching blocks S_(d1) to S_(d12) of the serial/parallel type A/D converter circuit, arranged in the form of matrix, to made the same perform a comparison between the respective reference voltages V₄₁ to V₅₅ (note, V₄₄, V₄₈, and V₅₂ are excluded) and the input analog signal V_(IN), it is determined for each column whether the number of the switching blocks for which the result of comparison that the analog signal V_(IN) is larger than the reference voltage is output is even or odd, and the conversion of lower data is carried out in accordance with the result of determination. Therefore, the conversions of data of the upper significant and lower significant data can be simultaneously carried out.

Accordingly, it becomes unnecessary to provide the sampling and holding circuit as in the conventional serial/parallel type A/D converter circuit, and also cumbersome circuit control is not required.

Also, the circuit can be constituted by a greatly reduced number of comparators in comparison with the parallel type A/D converter circuit requiring (2^(n) -1) comparators so as to obtain the n bits of conversion code, and therefore a reduction of the surface area of the chip and the power consumption can be achieved.

An explanation will now be made of a fifth embodiment of the present invention.

FIG. 17 is a structural view showing a fifth embodiment of the A/D converter circuit according to the present invention.

The essential point of difference of the present embodiment from the above-described embodiments resides in the constitution in which a plurality of sets of block comprising two adjoining switching blocks in the same column treated as one set are provided instead of performing the even/odd determination based on the combination of connection of the collector outputs of the transistor differential pairs constituting the respective switching blocks of the same column, the exclusive-OR of the two switching blocks of respective sets are obtained, respectively, and the results are subjected to so-called a wired-OR, whereby the even/odd determination is carried out.

In FIG. 17, EX₁ to EX₆ indicate the exclusive-OR gate constituting the even/odd determining circuit EOD_(1a) to EOD_(3a). These are connected as follows.

Namely, one input terminal of the exclusive-OR gate EX₁ is connected to the output terminal of the switching block S_(e1), and the other input terminal is connected to the output terminal of the switching block S_(e6) ; one input terminal of the exclusive-OR gate EX₆ is connected to the output terminal of the switching block S_(e7), and the other input terminal is connected to the output terminal of the switching block S_(e12) ; and the output terminals of the exclusive-OR gates EX₁ and EX₆ are connected to each other, whereby the even/odd determining circuit EOD_(1a) at the first column is constituted.

This even/odd determining circuit EOD_(1a) performs the wired-OR (logical OR) of the result of the exclusive-OR of the two gates at the middle point of connection between the output terminals of the exclusive-OR gates EX₁ and EX₆ and outputs the result thereof as the signal S_(EO1) indicating the result of even/odd determination at the first column to the buffer BD₂₁.

Also, one input terminal of the exclusive-OR gate EX₂ is connected to the output terminal of the switching block S_(e2), and the other input terminal is connected to the output terminal of the switching block S_(e5) ; one input terminal of the exclusive-OR gate EX₅ is connected to the output terminal of the switching block S_(e8), and the other input terminal is connected to the output terminal of the switching block S_(e11) ; and the output terminals of the exclusive-OR gates EX₂ and EX₅ are connected to each other, whereby the even/odd determining circuit EOD_(2a) at the second column is constituted.

This even/odd determining circuit EOD_(2a) performs the wired-OR (logical OR) of the result of the exclusive-OR of the two gates at the middle point of connection between the output terminals of the exclusive-OR gates EX₂ and EX₅ and outputs the result thereof as the signal S_(EO2) indicating the result of even/odd determination at the second column to the buffer B_(D2).

Further, one input terminal of the exclusive-OR gate EX₃ is connected to the output terminal of the switching block S_(B3), and the other input terminal is connected to the output terminal of the switching block S_(e4) ; one input terminal of the exclusive-OR gate EX₄ is connected to the output terminal of the switching block S_(e9), and the other input terminal is connected to the output terminal of the switching block S_(e10) ; and the output terminals of the exclusive-OR gates EX₃ and EX₄ are connected to each other, whereby the even/odd determining circuit EOD_(3a) at the third column is constituted.

This even/odd determining circuit EOD_(3a) performs the wired-OR (logical OR) of the result of the exclusive-OR of the two gates at the middle point of connection between the output terminals of the exclusive-OR gates EX₃ and EX₄ and outputs the result thereof as the signal S_(EO3) indicating the result of even/odd determination at the third column to the buffer BD₂₃.

Note that, in the structure of FIG. 17, the upper data comparators CU₂₁ to CU₂₃ are constituted not by complementary outputs, but by the usual single outputs, and are constituted so that the complementary output buffers BU₂₁ to BU₂₃ are provided on the input side of the next stage to this, that is on the input side of the AND gates AU₂₁ to AU₂₃, and further multiple output pin buffers MB_(U1) to MB_(U3) are provided between the outputs of the AND gates AU₂₁ to AU₂₃ and the inputs of the upper data encoders E_(U1), but the upper data conversion function is the same as that of the case of the first embodiment mentioned above.

Similarly, the circuit has a structure wherein multiple output pin buffers MB_(D1) to MB_(D3) are provided between the outputs of the AND gates AD₆₁ to AD₆₃ and the inputs of the lower data encoders E_(D1), but the lower significant data conversion function is the same as that of the case of the embodiment mentioned above.

Next, the operation by the structure of FIG. 17 will be explained using the timing chart of FIG. 18. Note that, the upper significant data conversion operation is essentially the same as that in the embodiment and therefore an explanation will be omitted.

In the same way as the case of the above-mentioned fourth embodiment, all switching blocks S_(e1) to S_(e12) are in the ON state at the time of the conversion operation, the input analog signal V_(IN) is compared with the corresponding reference voltages V₇₁ to V₇₃, V₇₅ to V₇₇, V₇₉ to V₈₁, and V₈₃ to V₈₅ of the fine quantization level divided by the reference resistance elements R₉₁ to R₁₀₆ at the respective switching blocks S_(e1) to S_(e12), respectively.

In the respective switching blocks S_(e1) to S_(e12), as the result of comparison, the output signals S₁₁₁ to S₁₂₂ are output as the "1" level if V_(IN) >reference voltage V, while the output signals S₇₁ to S₈₂ are output as the "0" level if V_(IN) ≦reference voltage V.

Accordingly, if for example V_(IN) <V₇₁, the signals S₁₁₁ to S₁₂₂ of the "0" level are output from all switching blocks S_(e1) to S_(e12).

For this reason, the signal levels input to both input terminals of all of the exclusive-OR gates EX₁ to EX₆ are "0".

Accordingly, since the output levels of all of the exclusive-OR gates EX₁ to EX₆ become "0", signals S_(EO1) to S_(EO3) are output from all of the even/odd determining circuits EOD_(1a) to EOD_(3a) as the "0" level, and also the output levels of the lower data side AND gates AD₆₁ to AD₆₃ become all "0".

As a result, [00] is output as the preceding output codes BD₅₅ and BD₅₆ of the lower significant 2 bits, from the lower data encoder E_(D1), and at this time, also the conversion code D₁ by the upper data encoder E_(U1) is [0], and therefore the preceding output codes BD₅₅ and BD₅₆ are not subjected to the inversion function at the inverted gate RV₁ and are output as the lower significant data conversion codes D₂ and D₃ while maintaining their levels [00] as they are.

If V₇₁ <V_(IN) <V₇₂, only the output signal S₁₁₁ of the switching block S_(e1) is output as the "1" level, and the output signals S₁₁₂ to S₁₂₂ of the remaining switching blocks S_(e1) to S_(e12) are output as the "0" level.

For this reason, only the output level of the exclusive-OR gate EX₁ at the first column from the left becomes "1", and the output levels of the other exclusive-OR gates EX₂ to EX₆ become "0".

Accordingly, the signal S_(EO1) is output as the "1" level from the even/odd determining circuit EOD₁, and signals S_(EO2) and S_(EO3) are output as the "0" level from the even/odd determining circuits EOD₂ and EOD₃.

By this, in the output levels of the AND gates AD₆₁ to AD₆₃, only the output of the AND gate AD₆₁ becomes "1", and the outputs of the other AND gates AD₆₂ and AD₆₃ become "0".

As a result, [01] is output as the preceding output codes BD₅₅ and BD₅₆ of the lower significant 2 bits from the lower data encoder E_(D1). At this time, also the conversion code D₁ by the upper data encoder E_(U1) is [0], and therefore the preceding output codes BD₅₅ and BD₅₆ are not subjected to the inversion function at the inverted gate RV₂₁ and are output as the lower significant data conversion codes D₂ and D₃ while maintaining their levels [01] as they are.

If V₇₂ <V_(IN) <V₇₃, only the output signals S₁₁₁ and S₁₁₂ of the switching blocks S_(B1) and S_(B2) are output as the "1" level, and the output signals S₁₁₃ to S₁₂₂ of the remaining switching blocks S_(e3) to S_(e12) are output as the "0" level.

For this reason, only the output levels of the exclusive-OR gates EX₁ and EX₂ become "1", and the output levels of the other exclusive-OR gates EX₃ to EX₆ become "0".

Accordingly, the signals S_(EO1) and S_(EO2) are output as the "1" level from the even/odd determining circuits EOD₁ and EOD₂, and the signal S_(EO3) is output as the "0" level from the even/odd determining circuit EOD₃.

By this, among the output levels of the AND gates AD₆₁ to AD₆₃, only the output of the AND gate AD₆₂ becomes "1", and the outputs of the other AND gates AU₂₁ and AU₂₃ become "0".

As a result, [10] is output as the preceding output codes BD₅₅ and BD₅₆ of the lower significant 2 bits from the lower data encoder E_(D1). At this time, also the conversion code D₁ by the upper data encoder E_(U1) is [0], and therefore the preceding output codes BD₅₅ and BD₅₆ are not subject to the inversion function at the inverted gate RV₁ and are output as the lower significant data conversion codes D₂ and D₃ while maintaining their levels [10] as they are.

If V₇₃ <V_(IN) <V₇₄, only the output signals S₁₁₁, S₁₁₂, and S₁₁₃ of the switching blocks S_(e1), S_(e2), and S_(e3) are output as the "1" level, and the output signals S₂₄ to S₃₂ of the remaining switching blocks S_(e4) to S_(e12) are output as the "0" level.

For this reason, only the output levels of the exclusive-OR gates EX₁, EX₂, and EX₃ become "1", and the output levels of the other exclusive-OR gates EX₄ to EX₆ become "0".

Accordingly, the signals S_(EO1) to S_(EO3) are output as the "1" level from the even/odd determining circuits EOD₁ to EOD₃.

By this, among the output levels of the AND gates AD₆₁ to AD₆₃, only the output of the AND gate AD₆₃ becomes "1", and the outputs of the other AND gates AU₂₁ and AU₂₂ become "0".

As a result, [11] is output as the preceding output codes BD₅₅ and BD₅₆ of the lower significant 2 bits from the lower data encoder E_(D1). At this time, also the conversion code D₁ by the upper data encoder E_(U1) is [0], and therefore the preceding output codes BD₅₅ and BD₅₆ are not subjected to the inversion function at the inverted gate RV₁ and are output as the lower significant data conversion codes D₂ and D₃ while maintaining their levels [11] as they are.

Note that, the case where V₇₄ <V_(IN) <V₇₅ is the same as the case where V₇₃ <V_(IN) <V₇₄, but at this time, the conversion code D₃ by the upper data encoder E_(U1) is [1], and therefore the preceding output codes BD₅₅ and BD₅₆ are subjected to the inversion function at the inverted gate RV₁ and output as the lower significant data conversion codes D₂ and D₃ with the level [00].

Further, if V₇₅ <V_(IN) <V₇₆, only the output signals S₁₁₁ to S₁₁₄ of the switching blocks S_(e1) to S_(e4) are output as the "1" level, and the output signals S₂₅ to S₃₂ of the remaining switching blocks S_(e5) to S_(e12) are output as the "0" level.

For this reason, only the output levels of the exclusive-OR gates EX₁ and EX₂ become "1", and the output levels of the other exclusive-OR gates EX₃ to EX₆ become "0".

Accordingly, the signals S_(EO1) and S_(EO2) are output as the "1" level from the even/odd determining circuits EOD₁ and EOD₂, and the signal S_(EO3) is output as the "0" level from the even/odd determining circuit EOD₃.

By this, in the output levels of the AND gates AD₆₁ to AD₆₃, only the output of the AND gate AD₆₂ becomes "1", and the outputs of the other AND gates AU₂₁ and AU₆₃ become "0".

As a result, [10] is output as the preceding output codes BD₂ and BD₃ of the lower significant 2 bits, from the lower data encoder E_(D1). At this time, the conversion code D₁ by the upper data encoder E_(U1) is [1], and therefore the preceding output codes BD₅₅ and BD₅₆ are subjected to the inversion function at the inverted gate RV₁ and output as the lower significant data conversion codes D₂ and D₃ with the level [01].

Further, if V₇₆ <V_(IN) <V₇₇, the output signals S₁₁₁ to S₁₁₅ of the switching blocks S_(e1) to S_(e5) are output as the "1" level, and the output signals S₁₁₆ to S₁₂₂ of the remaining switching blocks S_(e6) to S_(e12) are output as the "0" level.

For this reason, only the output level of the exclusive-OR gate EX₁ becomes "1", and the output levels of the other exclusive-OR gates EX₂ to EX₆ become "0".

Accordingly, the signal S_(EO1) is output as the "1" level from the even/odd determining circuit EOD₁, and the signals S_(EO2) and S_(EO3) are output as the "0" level from the even/odd determining circuits EOD₂ and EOD₃.

By this, in the output levels of the AND gates AD₆₁ to AD₆₃, only the output of the AND gate AD₆₁ becomes "1", and the outputs of the other AND gates AU₂₂ and AU₂₃ become "0".

As a result, [01] is output as the preceding output codes BD₅₅ and BD₅₆ of the lower significant 2 bits from the lower data encoder E_(D1). At this time, the conversion code D₁ by the upper data encoder E_(U1) is [1], and therefore the preceding output codes BD₅₅ and BD₅₆ are subjected to the inversion function at the inverted gate RV₁ and output as the lower significant data conversion codes D₂ and D₃ with the level [10].

If V₇₇ <V_(IN) <V₇₈, the output signals S₁₁₁ to S₁₁₆ of the switching blocks S_(e1) to S_(e6) are output as the "1" level, and the output signals S₁₁₇ to S₁₂₂ of the remaining switching blocks S_(e7) to S_(e12) are output as the "0" level.

For this reason, all of the output levels of the exclusive-OR gates EX₁ to EX₆ become "0".

Accordingly, the signals S_(EO1) to S_(EO3) are output as the "0" level from all of the even/odd determining circuits EOD_(1a) to EOD_(3a).

By this, in the output levels of the AND gates AD₆₁ to AD₆₃, the output levels of all of the AND gates AU₁ to AU₃ become "0".

As a result, [00] is output as the preceding output codes BD₅₅ and BD₅₆ of the lower significant 2 bits from the lower data encoder E_(D1). At this time, the conversion code D₁ by the upper data encoder E_(U1) is [1], and therefore the preceding output codes BD₅₅ and BD₅₆ are subjected to the inversion function at the inverted gate RV₁ and output as the lower significant data conversion codes D₂ and D₃ with the level [11].

Thereafter, in the case where V₇₈ <V_(IN) <V₈₂, the conversion code D₁ by the upper data encoder E_(U1) becomes [0], the conversion operation is the same as that in the case where V_(IN) <V₇₄ mentioned above, and in the case where V₈₂ <V_(IN), the conversion code D₃ by the upper data encoder E_(U1) becomes [1], and therefore the conversion operation becomes the same operation as that of the case where V₇₄ <V_(IN) <V₇₈.

As explained above, in the fifth embodiment, similar effects to those obtained in the above-mentioned fourth embodiment can be obtained.

Note that, in the above-mentioned fourth embodiment and fifth embodiment, an explanation was made taking as an example a circuit structure corresponding to 4-bit conversion, but needless to say the present invention can be applied also to the case of a larger number of bit conversion, and similar effects to those mentioned above can be obtained.

As explained above, according to the present invention, there are advantages that the increase of the power consumption and surface area of chip can be prevented, it is not necessary to provide the sampling and holding circuit, and the complication of the circuit control etc. can be prevented.

An explanation will be made next of a sixth embodiment of the present invention.

FIG. 19 is a circuit diagram showing the sixth embodiment of the A/D converter circuit according to the present invention.

Namely, 170 denotes a matrix circuit; 161 to 163 denote upper data comparators; 151 to 157 denote lower data comparators; 167 denotes an inverter; 150, an upper data encoder; 165, a lower data encoder; 166, a selection gate; OR₃₁ and OR₃₂ denote OR gates; and EXO₃₁ and EXO₃₂ denote exclusive-OR gates; respectively.

The upper data encoder 150 is constituted by an encoder line LN₁₅₆ generating the data for the redundant L (left) mode, an encoder line LN₁₅₇ generating the data for a non-redundant mode, and an encoder line LN₁₅₈ generating the data for the redundant R (right) mode.

Namely, in the upper data encoder 150, respective encoder lines LN₁₅₆ to LN₁₅₈ are set corresponding to a structure in which the columns of switching blocks shown with the hatching in the diagram, which detect the redundant bit among the switching blocks S_(f11) to S_(f17), S_(f21) to S_(f27), S_(f31) to S_(f37), and S_(f41) to S_(f47) arranged in the matrix circuit 170 are arranged so as to be positioned on both sides, i.e., the left side and right side, of the switching block columns outputting the conversion codes of the lower significant bits in FIG. 1.

FIG. 20 shows the correspondence between the outputs of the respective AND gates AU₃₁, AU₃₂, AU₃₃, and AU₃₄ of the upper data comparators 161 to 163, and the set output data code pattern of the respective encoder lines LN₁₅₆ to LN₁₅₇ of the upper data encoder 150.

The setting of the data is carried out so that, in accordance with the direction of transition of the reference voltage level by the respective reference resistance elements in the rows among the serially connected reference resistance element groups which are folded-back so that the number of rows becomes four, concretely an orientation (hereinafter referred to as a direction) of transition of the reference voltage from the low potential side to the high potential side, so that (data of redundant L mode≦(data of non-redundant mode)<(data of redundant R mode) or (data of redundant L mode)≧(data of non-redundant mode)>(data of redundant R mode) stands.

In the structure of FIG. 19, the first row from the bottom comprising the resistance elements R₁₃₃ to R₁₃₆ and the third row comprising the resistance elements R₁₂₅ to R₁₂₈ have the same direction, and the second row comprising the resistance elements R₁₂₉ to R₁₃₃ and the fourth row comprising the resistance elements R₁₂₁ to R₁₂₄ have the same direction.

Accordingly, the data setting level in the case where the AND gates AU₃₄ and AU₃₂ corresponding to the first row and the third row are at the "1" level is set so that (data of redundant L mode)≦(data of non-redundant mode)<(data of redundant R mode) stands.

Contrary to this, the data setting level in the case where the AND gates AU₃₃ and AU₃₁ corresponding to the second row and the fourth row are at the "1" level is set so that (data of redundant L mode)≧(data of non-redundant mode)>(data of redundant R mode) stands.

The lower data encoder 165 is constituted by a data line LN₁₅₁ generating the lower significant data BD₆₃ and BD₆₄ ; a selection line LN₁₅₂ generating the selection signal SEL₁ indicating that either of the outputs of the AND gates AD₇₁ and AD₇₂ of the lower data comparators 151 and 152 becomes "1"; a selection line LN₁₅₃ generating the selection signal SEL₂ indicating that either of the outputs of the AND gates AD₇₃ to AD₇₆ of the lower data comparators 153 to 156 becomes "1"; and a selection line LN₁₅₃ generating the selection signal SEL₁₃ indicating that either of the outputs of the AND gates AD₇₇ and AD₇₈ of the lower data comparator 157 becomes "1".

FIG. 21 shows the correspondence between the outputs of the AND gates AD₇₁ to AD₇₈ of the lower data comparators 151 to 157, output data of the lower data encoder 165, and the selection signal.

The selection gate 166 is constituted by AND gates A₄₁ to A₄₆, selects one upper significant data from among the respective upper significant data of the redundant L mode, non-redundant mode, and the redundant R mode output from the upper data encoder 150 using the selection signals SEL₁₁ to SEL₁₃ output from the lower data encoder 166, and outputs the same as the conversion codes D₁ and D₂ via the OR gates OR₃₁ and OR₃₂.

Concretely, one input terminal of the AND gate A₄₁ is connected to one line (upper significant side) of the encoder line LN₁₅₆ generating the data for the redundant L mode of the upper data encoder 150, and the other input terminal is connected to the selection line LN₁₅₂ outputting the selection signal SEL₁₁ of the lower data encoder 165.

One input terminal of the AND gate A₄₂ is connected to one line (upper significant side) of the encoder line LN₁₅₇ generating the data for the non-redundant mode of the upper data encoder 150, and the other input terminal is connected to the selection line LN₁₅₃ outputting the selection signal SEL₁₂ of the lower data encoder 165.

One input terminal of the AND gate A₄₃ is connected to one line (upper data side) of the encoder line LN₁₅₈ generating the data for the redundant R mode of the upper data encoder 150, and the other input terminal is connected to the selection line LN₁₅₄ outputting the selection signal SEL₁₃ of the lower data encoder 165.

The outputs of these AND gates A₄₁ to A₄₃ are connected to the input terminals of the 3-input OR gate OR₃₁.

Further, one input terminal of the AND gate A₄₄ is connected to the other line (lower data side) of the encoder line LN₁₅₆ generating the data for the redundant L mode of the upper data encoder 150, and the other input terminal is connected to the selection line LN₁₅₂ outputting the selection signal SEL₁₁ of the lower data encoder 165.

One input terminal of the AND gate A₄₅ is connected to the other line (lower data side) of the encoder line LN₁₅₇ generating the data for the non-redundant mode of the upper data encoder 150, and the other input terminal is connected to the selection line LN₁₅₃ outputting the selection signal SEL₁₂ of the lower data encoder 165.

One input terminal of the AND gate A₄₆ is connected to the other line (lower data side) of the encoder line LN₁₅₈ generating the data for the redundant R mode of the upper data encoder 150, and the other input terminal is connected to the selection line LN₁₅₄ outputting the selection signal SEL₁₃ of the lower data encoder 165.

The outputs of these AND gates A₄₄ to A₄₆ are connected to respective input terminals of the 3-input OR gate OR₃₂.

The exclusive-OR gate EXO₃₁ obtains the exclusive-OR between the lower significant data BD₆₃ output from one line of the data line LN₁₅₁ of the lower data encoder 165 and the signal obtained by inverting the output level of the AND gate AU₃₁ or AU₃₃ of the upper data comparators 151 and 153 by the inverter 167 and outputs the result thereof as the lower data conversion code D₃.

The exclusive-OR gate EXO₃₂ obtains the exclusive-OR between the lower significant data BD₆₄ output from the other line of the data line LN₁₅₁ of the lower data encoder 165 and the signal obtained by inverting the output level of the AND gate AU₃₁ or AU₃₃ of the upper data comparators 161 and 163 by the inverter 167 and outputs the result thereof as the lower data conversion code D₄.

In these processings, the direction of application of the reference voltage is reverse between the first row and the third row along with the folded-back arrangement of the reference resistance columns in the second row and the fourth row of the switching blocks in the matrix circuit 170, and, therefore when the second row and the fourth row are selected by the control signal, it is carried out so as to invert the levels of the lower significant data BD₆₃ and BD₆₄ and output the same as the lower significant data conversion codes D₃ and D₄.

Next, an explanation will be made of the operation by the above-described structure.

For example, when the sampling voltage V_(S) of the sampled analog signal is represented as V_(RB) <V_(S) <V₉₃, the outputs of the comparators CU of the upper data comparators 161, 162, and 163 become all "L", so that the digital signals are output, i.e., "0" is output from the AND gates AU₃₁ to AU₃₃, and "1" is output from the AU₃₄, respectively.

As a result, a digital signal such as [0001] is input to the upper data encoder 150. At the upper data encoder 150, using a so-called wired-OR circuit, [00] is generated in the two columns of the encoder line [LN₁₅₆ ] generating the redundant L mode data; [00] is generated in the two columns of the encoder line [LN₁₅₇ ] generating the non-redundant mode data; and [01] is generated in the two columns of the encoder line [LN₁₅₈ ] generating the redundant R mode data; respectively, which are output to the selection gate 166.

Also, when the sampling voltage V_(S) is represented as V₉₃ <V_(S) <V₉₂, similarly the digital signals are output, i.e., "0" is output from the upper significant side AND gates AU₃₁, AU₃₂, and AU₃₄, and "1" is output from the AU₃₃, respectively.

As a result, a digital signal such as [0010] is input to the upper data encoder 150, and the upper significant data is output, i.e., [10] is output from the line [LN₁₅₆ ]; [01] is output from the line [LN₁₅₇ ]; and [00] is output from the line [LN₁₅₈ ], to the selection gate 166.

Further, when the sampling voltage V_(S) is represented as V₉₂ <V_(S) <V₉₁, the digital signals are output, i.e., "0" is output from the upper data side AND gates AU₃₁, AU₃₃, and AU₃₄, and "1" is output from the AU₉₂, respectively.

As a result, a digital signal such as [0100] is input to the upper data encoder 100, and the upper significant data is output, i.e., [01] is output from the line [LN₁₅₆ ]; [10] is output from the line [LN₁₅₇ ]; and [11] is output from the line [LN₁₅₈ ], to the selection gate 166.

Similarly, when the sampling voltage V_(S) is represented as V₉₁ <V_(S) <V_(RT), the digital signals are output, i.e., "0" is output from the upper data side AND gates AU₃₂, AU₃₃, and AU₃₄, and "1" is output from the AU₃₁, respectively.

As a result, a digital signal such as [1000] is input to the upper data encoder 150, and the upper significant data is output, i.e., [11] is output from the line [LN₁₅₆ ]; [11] is output from the line [LN₁₅₇ ]; and [10] is output from the line [LN₁₅₆ ], to the selection gate 166.

In parallel with this, the transistors Q₁₅₃ of the respective switching blocks of the matrix circuit 170 connected to the control lines (x₃₁, x₃₂, x₃₃, and x₃₄) at which the digital output signal has become "1" among the respective AND gates AU.sub.(31, 32, 33, 34) are controlled to turn ON in units of rows, and further a fine digitization of the quantization level is executed.

For example, when only the output of the AND gate AU₃₃ becomes the "1" level, the transistors Q₁₅₃ of the switching blocks S_(f31) to S_(f37) become ON, so that the reference voltages divided by the reference resistors R₁₂₇ to R₁₃₃ and the sampling voltage V_(S) are differentially amplified at the switching blocks S₃₁ to S₃₇ and compared by the lower data comparators 151 to 157.

Similarly, when the output of the AND gate AU₃₂ is at the "1" level, the switching blocks S_(f21) to S_(f27) are activated, so that a differential amplification operation is performed, and the comparison by the lower data comparators 151 to 157 is carried out.

In this way, in the lower data conversion codes, the sampled voltage V_(S) and the reference voltage divided by the reference resistance of that row are compared in units of rows of the switching blocks, so that the digital signal will be output from the AND gates AD₇₁ to AD₇₇ and AD₇₈ of the lower data comparators 151 to 157 as shown in FIG. 21.

At this time, where the level of the analog signal outputting the upper significant 2 bits of the conversion code is not changed from that of the analog signal when the lower significant 2 bits of the conversion code are output, the signal of the "1" level is output from one AND gate among the AND gates AD₇₃ to AD₇₆ of the lower data comparators 153 to 156 to the lower data encoder 165.

In this case, in the lower data encoder 165, only the selection line LN₁₅₃ becomes "1". As a result, the selection signal SEL₁₂ is input to the selection gate 166 as the "1" level, and the selection signals SEL₁₁ and SEL₁₃ are input to the selection gate 166 as the "0" level.

In the selection gate 166, along with the fact that only the selection signal SEL₁₂ is input as the "1" level, only the AND gates A₄₂ and A₄₅ are activated.

To these AND gates A₄₂ and A₄₅, the upper data side and lower data side of the upper significant data for the non-redundant mode generated in the line LN₁₅₇ of the upper data encoder 150 are respectively supplied.

Accordingly, in the selection gate 166, the respective bits of the upper significant data at the non-redundant mode are selected, and as a result, they are output as the upper significant data conversion codes D₁ and D₂ via the OR gates OR₃₁ and OR₃₂.

Concretely, when the sampling voltage V_(S) of the analog signal V_(IN) is defined as V_(RB) <V_(S) <V₉₃, the upper data conversion codes [D₁, D₂ ] are output as [00]; when V₉₃ <V_(S) <V₉₂ stands, the upper data conversion codes [D₁, D₂ ] are output as [01]; when V₉₂ <V_(S) <V₉₁ stands, the upper data conversion codes [D₁, D₂ ] are output as [10]; and when V₉₁ <V_(S) <V_(RT) stands, the upper significant data conversion codes [D₁, D₂ ] are output as [11].

Also, in the selection gate 165, when the output of the AND gate A_(D3) of the lower data comparator 153 is "1", the lower significant data BD₆₃ and BD₆₄ are generated as [11]; when the output of the AND gate AD₇₃ of the lower data comparator 154 is "1", the lower significant data BD₆₃ and BD₆₄ are generated as [10]; when the output of the AND gate AD₇₅ of the lower data comparator 155 is "1", the lower significant data BD₆₃ and BD₆₄ are generated as [01]; when the output of the AND gate AD₇₆ of the lower data comparator 156 is "1", the lower significant data BD₆₃ and BD₆₄ are generated as [00]; and the data BD₆₃ is output to the exclusive-OR gate EXO₃₁, and the data BD₆₄ is output to the exclusive-OR gate EXO₃₂ .

In the exclusive-OR gates EXO₃₁ and EXO₃₂, when V_(RB) <V_(S) <V₉₃ and V₉₂ <V_(S) <V₉₁ stand, that is where the switching blocks S_(f41) to S_(f47) and S_(f21) to S_(f27) of the first row and third row from the bottom of the matrix circuit 170 are selected, since the direction of application of the reference voltage is the forward direction, the levels of the lower significant data are output as the lower significant data conversion codes D₃ and D₄ while inverting the output level of the lower data encoder 165.

Contrary to this, when V₉₃ <V_(S) <V₉₂ and V₉₁ <V_(S) <V_(RT) stand, that is where the switching blocks S_(f31) to S_(f37) and S_(f11) to S_(f17) of the second row and fourth row from the bottom of the matrix circuit 170 are selected, since the direction of application of the reference voltage is the inverse direction, the levels of the lower significant data are held at the output level of the lower data encoder 165 as they are and output as the lower significant data conversion codes D₃ and D₄.

Also, at the time of conversion, in a case where V₉₃ <V_(IN) <V₉₂ when the upper significant 2 bits D₁ and D₂ are digitized and V₉₂ <V_(IN) when the lower significant 2 bits D₃ and D₄ are digitized; or in a case where V₉₂ <V_(IN) <V₉₁ when the upper significant 2 bits D₁ and D₂ are digitized and V_(IN) <V₉₂ when the lower significant 2 bits D₃ and D₄ are digitized, a signal of the "1" level is output from one AND gate among the AND gates AD₇₁ and AD₇₂ of the lower data comparators 151 and 152 to the lower data encoder 165.

In this case, in the lower data encoder 165, only the selection line LN₁₅₂ becomes "1". As a result, the selection signal SEL₁₁ is input to the selection gate 166 as the "1" level, and the selection signals SEL₁₂ and SEL₁₃ are input to the selection gate 166 as the "0" level.

In the selection gate 166, along with the fact that only the selection signal SEL₁₁ is input as the "1" level, only the AND gates A₄₁ and A₄₄ are activated.

To these AND gates A₄₁ and A₄₄, the upper data side and lower data side of the upper significant data for the redundant n mode generated in the line LN₁₅₆ of the upper data encoder 150 are respectively supplied.

Accordingly, in the selection gate 166, the respective bits of the upper significant data at the redundant n mode are selected, and as a result, they are output as the upper significant data conversion codes D₁ and D₂ via the OR gates OR₃₁ and OR₃₂.

Concretely, when the sampling voltage V_(S) of the analog signal V_(IN) is defined as V_(RB) <V_(S) <V₉₃, the upper data conversion codes [D₁, D₂ ] are output as [00]; when V₉₃ <V_(S) <V₉₂ stands, the upper data conversion codes [D₁, D₂ ] are output as [10]; when V₉₂ <V_(S) <V₉₁ stands, the upper data conversion codes [D₁, D₂ ] are output as [01]; and when V₉₁ <V_(S) <V_(RT) stands, the upper data conversion codes [D₁, D₂ ] are output as [11].

Namely, at this redundant L mode, when V₉₃ <V_(S) <V₉₂ (when the output of the AND gate AU₃₃ is "1"), the upper data conversion code [D₁, D₂ ] is corrected to a code [10] which is larger than the output code [01] in the case of the non-redundancy by "1" and output; and when V₉₂ <V_(S) <V₉₁ (when the output of the AND gate AU₃₂ is "1"), the upper data conversion code [D₁, D₂ ] is corrected to a code [01] which is smaller than the output code [10] in the case of the non-redundancy by "1" and output.

Also, in the selection gate 165, when the output of the AND gate AD₇₁ of the lower data comparator 151 is "1", the lower significant data BD₆₃ and BD₆₄ are generated as [01]; and when the output of the AND gate AD₇₂ of the lower data comparator 152 is "1", the lower significant data BD₆₃ and BD₆₄ are generated as [00], so that the data BD₆₃ is output to the exclusive OR gate EXO₃₁, the data BD₆₃ is output to the exclusive-OR gate EXO₃₂, which is subjected to the predetermined level adjustment function here and output as the lower data conversion codes D₃ and D₄.

Also, at the time of conversion, in a case where V_(IN) <V₉₃ when the upper significant 2 bits D₁ and D₂ are digitized and V₉₃ <V_(IN) when the lower significant 2 bits D₃ and D₄ are digitized; or in a case where V₉₃ <V_(IN) <V₉₂ when the upper significant 2 bits D₁ and D₂ are digitized and V_(IN) <V₉₃ when the lower significant 2 bits D₃ and D₄ are digitized; or in a case where V₉₂ <V_(IN) <V₉₁ when the upper significant 2 bits D₁ and D₂ are digitized and V₁ <V_(IN) when the lower significant 2 bits D₃ and D₄ are digitized; or in a case where V₁ <V_(IN) when the upper significant 2 bits D₁ and D₂ are digitized and V_(IN) <V₉₁ when the lower significant 2 bits D₃ and D₄ are digitized, a signal of the "1" level is output from one AND gate among the AND gate AD₇₇ and AND gate AD₇₈ of the lower data comparator 157 to the lower data encoder 165.

In this case, in the lower data encoder 165, only the selection line LN₁₅₄ becomes "1". As a result, the selection signal SEL₁₃ is input to the selection gate 166 as the "1" level, and the selection signals SEL₁₁ and SEL₁₂ are input to the selection gate 166 as the "0" level.

In the selection gate 166, along with the fact that only the selection signal SEL₁₃ is input as the "1" level, only the AND gates A₄₃ and A₄₆ are activated.

To these AND gates A₄₃ and A₄₆, the upper data side and lower data side of the upper significant data for the redundant R mode generated in the line LN₁₀₃ of the upper data encoder 150 are respectively supplied.

Accordingly, in the selection gate 166, the respective bits of the upper significant data at the redundant R mode are selected, and as a result, they are output as the upper significant data conversion codes D₁ and D₂ via the OR gates OR₃₁ and OR₃₂.

Concretely, when the sampling voltage V_(S) of the analog signal V_(IN) is defined as V_(RB) <V_(S) <V₉₃, the upper data conversion codes [D₁, D₂ ] are output as [01]; when V₉₃ <V_(S) <V₉₂ stands, the upper data conversion codes [D₁, D₂ ] are output as [00]; when V₉₂ <V_(S) <V₉₁ stands, the upper data conversion codes [D₁, D₂ ] are output as [11]; and when V₉₁ <V_(S) <V_(RT) stands, the upper data conversion codes [D₁, D₂ ] are output as [10].

Namely, at this redundant R mode, when V_(RB) <V_(S) <V₉₃ (when the output of the AND gate A_(U4) is "1"), the upper data conversion code [D₁, D₂ ] is corrected to a code [01] which is larger than the output code [00] in the case of the non-redundancy by "1" and output, and when V₉₃ <V_(S) <V₉₂ (when the output of the AND gate AU₃₃ is "1"), the upper data conversion code [D₁, D₂ ] is corrected to a code [00] which is smaller than the output code [01] in the case of the non-redundancy by "1" and output; and when V₉₂ <V_(S) <V₉₁ (when the output of the AND gate AU₃₂ is "1"), the upper data conversion code [D₁, D₂ ] is corrected to a code [11] which is larger than the output code [10] in the case of the non-redundancy by "1" and output, and when V₉₁ <V_(S) <V_(RT) (when the output of the AND gate AU₃₁ is "1"), the upper data conversion code [D₁, D₂ ] is corrected to a code [10] which is smaller than the output code [11] in the case of the non-redundancy by "1" and output.

Also, in the selection gate 165, when the output of the AND gate AD₇₇ of the lower data comparator 157 is "1", the lower significant data BD₆₃ and BD₆₄ are generated as [11]; and when the output of the AND gate AD₇₈ of the lower data comparator 152 is "1", the lower significant data BD₆₃ and BD₆₄ are generated as [10], so that the data BD₆₃ is output to the exclusive OR gate EXO₃₁, the data BD₆₄ is output to the exclusive-OR gate EXO₃₂, which is subjected to the predetermined level adjustment function here and output as the lower data conversion codes D₃ and D₄.

As explained above, according to the present embodiment, so as to correct the upper significant data, the output data level of the encoder 150 and the output level of the selection signal of the lower data encoder 165 were set in advance so as to select an appropriate data from among three data, i.e., the left redundant data (data to be selected by the lower data encoder in the left part of the resistance column), normal data, and the right redundant data, and therefore it is possible to use the selection signal directly for the selection of the upper significant data without the use of the inverted gate and inhibit gate as in the conventional circuit.

Accordingly, an A/D converter circuit with which the input of the selection signal to the selection gate 166 is not delayed in relative to the output of the upper data encoder 150, the increase of speed of conversion processing can be achieved, and the decrease of the chip area and reduction of the power consumption can be achieved can be realized.

Note that, in the present embodiment, an explanation was made taking as an example an A/D converter circuit for four bits, but needless to say the present invention can be applied to a A/D converter circuit for more bits.

As explained above, according to the present invention, there are advantages that the inverted gate and inhibit gate which have been conventionally necessary become unnecessary, the increase of speed of conversion processing can be achieved, and the decrease of the chip area and reduction of the power consumption can be achieved.

An explanation will be made next of a seventh embodiment of the present invention.

FIGS. 22A-22C are circuit diagrams showing the seventh embodiment of the A/D converter circuit according to the present invention.

In FIG. 22, 180 denotes a matrix circuit; 181 and 182 denote upper data comparators as the data change point detection circuits; 183, an upper data encoder; 191 to 197 denote lower data comparators; 185, a lower data encoder; 186, a selection gate; 184, an inverter; R₁₄₁ to R₁₅₆ denote reference resistance elements; B_(U41) to B_(U43) and B_(D51) to B_(D58) denote multiple output pin buffers; OR₄₁ and OR₄₂ denote OR gates; and EXO₄₁ and EXO₄₂ denote exclusive-OR gates; respectively.

The matrix circuit 180 is constituted by the arrangement of 21 switching blocks S_(g11) to S_(g17), S_(g21) to S_(g27), and S_(g31) to S_(g37) in the form of a matrix comprising three rows and seven columns.

The respective switching blocks S_(g11) to S_(g17), S_(g21) to S_(g27), and S_(g31) to S_(g37) are constituted by differential type amplifiers comprising the npn-type transistors Q₁₆₁, Q₁₆₂, and Q₁₆₃.

A reference voltage obtained by dividing the reference voltages V_(RT) to V_(RB) by the reference resistance elements R₁₄₁ to R₁₅₆ is supplied to the base of one side transistors Q₁₆₁ constituting a so-called differential pair of the respective switching blocks, and analog signals V_(IN) which are to be converted to the digital code are supplied to the base of the other side transistors Q₁₆₂, respectively.

Also, the emitters of the transistors Q₁₆₁ and Q₁₆₂ are connected to each other, and the middle point of connection thereof is connected to the current source I via the transistor Q₁₆₃ switched by the control signals x₄₁ and x₄₂, respectively.

To the collectors of the transistors Q₁₆₁ and Q₁₆₃, the power source voltage V_(DD) is supplied via the resistance element r, the output of which is input to the comparators C_(D51) to C_(D57) of the seven lower data comparators 191 to 197 as mentioned later, which act also as the initial stage amplifiers of the lower data comparators 191 to 197.

Also, the collectors of the transistors Q₁₆₁ and Q₁₆₂ of the switching block at the second row from the bottom of the diagram are connected to the line in an opposite direction to that for the collector output of the transistors Q₁₆₁ and Q₁₆₂ of the switching blocks at the first row and third row, and a measure is devised so that the line of the serial reference resistance elements R₁₄₁ to R₁₅₆ to which the reference potentials V_(RT) to V_(RB) are applied can be formed by folding-back.

The reference resistance elements R₁₄₁ to R₁₅₆ are serially connected between the two reference potentials V_(RT) and V_(RB) and arranged by folding-back so as to extend over a predetermined number of rows, e.g., five rows in the present embodiment, to correspond to the matrix arrangement of the switching blocks in the matrix circuit 184.

Concretely, each two resistance elements R₁₅₆ and R₁₅₅ and R₁₄₂ and R₁₄₁ are serially connected to the first row and the fifth row from the bottom in the diagram, and the resistance elements R₁₅₄ to R₁₅₁, R₁₅₀ to R₁₄₇, and R₁₄₆ to R₁₄₃ are serially connected to the second row to the fourth row, respectively.

Viewing this folding-back arrangement of the resistance element columns from the reference potential V_(RB) terminal side positioned on the left end and lower end side of the matrix circuit 180, the wiring pattern extended in the right direction in the diagram is folded-back between the switching block column of the fourth column from the left in the diagram and the switching block column of the fifth column, and two resistance elements R₁₅₆ and R₁₅₅ are connected in series, whereby the first row of the resistance column is constituted.

The resistance column at the first row is folded-back between the switching block column of the third column and the switching block column of the second column, and four resistance elements R₁₅₄ to R₁₅₁ are connected in series between the switching block rows of the first row and the second row and, corresponding to the arrangement position of the switching blocks S_(g33) to S_(g36) of the first row, whereby the resistance column of the second row is constituted.

The resistance column of the second row is folded-back between the switching block column of the fifth column and the switching block column of the sixth column, and four resistance elements R₁₅₀ to R₁₄₇ are connected in series between the switching block rows at the first row and the second row and, corresponding to the arrangement position of the switching blocks S_(g26) to S_(g23) at the second row, whereby the resistance column of the third row is constituted.

The resistance column of the third row is folded-back between the switching block column of the third column and the switching block column of the second column, and four resistance elements R₁₄₆ to R₁₄₃ are connected in series corresponding to the arrangement position of the switching blocks S₁₃ to S₁₆ at the third row, whereby the resistance column of the fourth row is constituted.

The resistance column of the fourth row is folded-back between the switching block column of the fifth column and the switching block column of the sixth column, four resistance elements R₁₄₂ to R₁₄₁ are connected in series corresponding to the arrangement position of the switching blocks S_(g16) to S_(g15) at the third row, and one end of the resistance element R₁ is connected to the terminal of the reference potential V_(RT), whereby the resistance column of the fifth row is constituted.

Namely, the resistance columns at the first row and the fifth row are arranged at a deviation of a half cycle with respect to the resistance columns at the second row to the fourth row so that the position exhibiting the lowest value of the reference voltage (connection point between the reference potential V_(RB) terminal and the resistance element R₁₅₆) and the position exhibiting the highest value (connection point between the reference potential V_(RT) terminal and the resistance element R₁₄₁) are positioned at an intermediate point in the row direction of the switching blocks arranged in the form of the matrix.

Such a structure of arrangement of the resistance columns is made for the purpose of dividing the switching block columns comprising seven columns into the group comprising the switching block columns from the first column to the fourth column and the group of the switching block columns from the fifth column to the seventh column of the switching point between the upper data and lower data as will be mentioned later.

Also, the voltages V₁₂₈ and V₁₂₇ generated between the rows of the fourth row and the third row and between the rows of the third row and the second row of the resistance columns are supplied to the upper data comparators 181 and 182 as the reference voltages obtained by dividing the reference potentials V_(RT) to V_(RB) by rough quantization, respectively.

In the structure of FIG. 1, when assuming that the voltage between the reference potentials V_(RT) to V_(RB) is V_(REF), the respective reference voltages V₁₂₈ and V₁₂₇ become the following values, respectively:

    V.sub.128 =(10/16)·V.sub.REF

    V.sub.127 =(6/16)·V.sub.REF

Further, wiring is carried out so that the respective reference voltages V₁₁₁ to V₁₂₅ divided by the reference resistance elements R₁₄₁ to R₁₅₆ are supplied to the base of the transistor Q₁₆₁ of the predetermined switching block.

Concretely, a reference voltage V₁₁₁ [=(15/16)·V_(REF) ] generated at the middle point of connection between the resistance elements R₁₄₁ and R₁₄₂ is supplied to the base of the transistor Q₁₆₁ of the switching block S_(g17).

A reference voltage V₁₁₂ [=(14/16)·V_(REF) ] generated at the connection between the resistance elements R₁₄₂ and R₁₄₃ is supplied to the base of the transistor Q₁₆₁ of the switching block S_(g16).

A reference voltage V₁₁₃ [=(13/16)·V_(REF) ] generated at the connection between the resistance elements R₁₄₃ and R₁₄₄ is supplied to the base of the transistor Q₁₆₁ of the switching block S_(g15).

A reference voltage V₁₁₄ [=(12/16)·V_(REF) ] generated at the connection between the resistance elements R₁₄₄ and R₁₄₅ is supplied to the base of the transistor Q₁₆₁ of the switching block S_(g14).

A reference voltage V₁₁₅ [=(11/16)·V_(REF) ] generated at the connection between the resistance elements R₁₄₅ and R₁₄₆ is supplied to the bases of the transistors Q₁₆₁ of the switching blocks S_(g13) and S_(g21).

A reference voltage V₁₁₆ [=V₁₂₈ =(10/16)·V_(REF) ] generated at the connection between the resistance elements R₁₄₆ and R₁₄₇ is supplied to the bases of the transistors Q₁₆₁ of the switching blocks S_(g12) and S_(g22).

A reference voltage V₁₁₇ [=(9/16)·V_(REF) ] generated at the connection between the resistance elements R₁₄₇ and R₁₄₈ is supplied to the bases of the transistors Q₁₆₁ of the switching blocks S_(g4) and S_(g23).

A reference voltage V₁₁₈ [=(8/16)·V_(REF) ] generated at the connection between the resistance elements R₁₄₈ and R₁₄₉ is supplied to the base of the transistor Q₁₆₁ of the switching block S_(g24).

A reference voltage V₁₁₉ [=(7/16)·V_(REF) ] generated at the connection between the resistance elements R₁₄₉ and R₁₅₀ is supplied to the bases of the transistors Q₁₆₁ of the switching blocks S_(g25) and S_(g37).

A reference voltage V₁₂₀ [=V₁₂₇ =(6/16)·V_(REF) ] generated at the connection between the resistance elements R₁₅₀ and R₁₅₁ is supplied to the bases of the transistors Q₁₆₁ of the switching blocks S_(g26) and S_(g36).

A reference voltage V₁₂₁ [=(5/16)·V_(REF) ] generated at the connection between the resistance elements R₁₅₁ and R₁₅₂ is supplied to the bases of the transistors Q₁₆₁ of the switching blocks S_(g27) and S_(g35).

A reference voltage V₁₂₂ [=(4/16)·V_(REF) ] generated at the connection between the resistance elements R₁₅₂ and R₁₅₃ is supplied to the base of the transistor Q₁₆₁ of the switching block S_(g34).

A reference voltage V₁₂₃ [=(3/16)·V_(REF) ] generated at the connection between the resistance elements R₁₅₃ and R₁₅₄ is supplied to the base of the transistor Q₁₆₁ of the switching block S_(g33).

A reference voltage V₁₂₄ [=(2/16)·V_(REF) ] generated at the connection between the resistance elements R₁₅₄ and R₁₅₅ is supplied to the base of the transistor Q₁₆₁ of the switching block S_(g32).

A reference voltage V₁₂₅ [=(1/16)·V_(REF) ] generated at the connection between the resistance elements R₁₅₅ and R₁₅₆ is supplied to the base of the transistor Q₁₆₁ of the switching block S_(g31).

The upper data comparators 181 and 182 respectively are provided with comparators C_(U41) and C_(U42), complementary-type output amplifiers CA₅₈, 59, and AND gates AU₄₁ and AU₄₂. Note that, for the reasons described later, the upper data comparator 181 acts also as the upper data comparator for the uppermost row, and the upper data comparator 182 acts also as the upper data comparator for the lowermost row.

An analog signal V_(IN) is supplied to one input of the comparator CU₄₁ of the upper data comparator 181, and a reference voltage V₁₂₈ [=(10/16)·V_(REF) ] obtained by dividing the reference potentials V_(RT) to V_(RB) by the rough quantization is supplied to the other input.

The analog signal V_(IN) is supplied to one input of the comparator CU₄₂ of the upper data comparator 182, and a reference voltage V₁₂₇ [=(6/16)·V_(REF) ] obtained by dividing the reference potentials V_(RT) to V_(RB) by the rough quantization is supplied to the other input.

The output of the comparator CU₄₁ of the upper data comparator 181 is connected to the input of the output amplifier CA₅₈, the positive output thereof is connected to both inputs of a 2-input AND gate AU₄₁, and the negative output is connected to one input of the 2-input AND gate AU₄₂ of the upper data comparator 182.

The output of comparator CU₄₂ of the upper data comparator 182 is connected to the input of the output amplifier CA₄₂, the positive output thereof is connected to the other input of the 2-input AND gate AU₄₂, and the negative output is connected to the both inputs of the 2-input AND gate AU₄₃.

The outputs of the respective comparators CU₄₁ and CU₄₂ of the upper data comparators 181 and 182 constituted in this way become the level of "H" or "L" corresponding to the level of the sampled analog signal V_(IN), and only one among the respective AND gates AU₄₁ to AU₄₃ outputs the "1" level.

The output of the AND gate AU₄₁ of the upper data comparator 181 is connected via the buffer BU₄₁ to the upper data encoder 183 and, at the same time, connected to the bases of the transistors Q₁₆₃ of the switching blocks S_(g11) to S_(g17).

The output of the AND gate AU₄₂ of the upper data comparator 182 is connected via the buffer BU₄₂ to the upper data encoder 183 and, at the same time, connected to the bases of the transistors Q₁₆₃ of the switching blocks S_(g21) to S_(g27) and connected to the input of the inverter 184 via the buffer.

The AND gate AU₄₃ of the upper data comparator 183 is connected via the buffer BU₄₃ to the upper data encoder 183 and, at the same time, connected to the bases of the transistors Q₁₆₃ of the switching blocks S_(g31) to S_(g37).

The upper data encoder 183 is constituted by an encoder line LN₁₆₁ generating the data for an L (left) mode, and an encoder line LN₁₆₂ generating the data for an R (right) mode.

Namely, in the upper data encoder 183, respective encoder lines LN₁₆₁ and LN₁₆₂ are set up corresponding to a first group of from the first column to the fourth column arranged on the left side from the center of the matrix circuit 180, and a second group of from the fifth column to the seventh column arranged on the right side among the switching blocks S_(g11) to S_(g17), S_(g21) to S_(g27) and S_(g31) to S_(g37) arranged in the matrix circuit 180.

FIG. 23 shows the correspondence between the outputs of the respective AND gates AU₄₁, AU₄₂, and AU₄₃ of the upper data comparators 181 and 182 and the set output data code pattern of the respective encoder lines LN₁₆₁ and LN₁₄₂ of the upper data encoder 183.

The data is set in a manner that, in accordance with the direction of transition of the reference voltage level by the respective reference resistance elements in the first row to the fifth row (the second row to the fourth row in the present embodiment) from the bottom among the serially connected reference resistance element groups which are folded-back so that the number of rows becomes five, concretely an orientation (hereinafter referred to as a direction) of transition of the reference voltage from the low potential side to the high potential side, so that (data of L mode)<(data of R mode) and (data of L mode)<(data of R mode) stand.

In the structure of FIG. 22, the first row from the bottom comprising the resistance elements R₁₅₆ and R₁₅₅, the third row comprising the resistance elements R₁₅₀ to R₁₄₇, and the fifth row comprising the resistance elements R₁₄₂ and R₁₄₁ have the same direction, and the second row comprising the resistance elements R₁₅₄ to R₁₅₁ and the fourth row comprising the resistance elements R₁₄₆ to R₁₄₃ have the same direction.

Accordingly, the data setting level in the case where the AND gate AU₄₂ corresponding to the third row is at the "1" level is set so that (data of L mode)>(data of R mode) stands.

Contrary to this, the data setting level in the case where the AND gates AU₄₃ and AU₄₁ corresponding to the second row and the fourth row are at the "1" level is set so that (data of L mode)<(data of R mode) stands.

The lower data comparators 191 to 197 are respectively provided with comparators CD₅₁ to CD₅₇, complementary-type output amplifiers CA₅₁ to 57, and AND gates AD₈₁ to AD₈₇.

To one input of the comparator CD₅₁ of the lower data comparator 191 is supplied the collector output of the transistor Q₁₆₁ of the switching block S_(g21) at the first column of the matrix circuit 180 and the collector output of the transistor Q₁₆₂ of the switching blocks S_(g11) and S_(g31), and to the other input is supplied the collector outputs of the transistors Q₁₆₁ of the switching blocks S_(g11) and S_(g31) and the collector output of the transistor Q₁₆₂ of the switching block S_(g21).

To one input of the comparator CD₅₂ of the lower data comparator 192 is supplied the collector output of the transistor Q₁₆₁ of the switching block S_(g22) at the second column of the matrix circuit 180 and the collector output of the transistor Q₁₆₂ of the switching blocks S_(g12) and S_(g32), and to the other input is supplied the collector outputs of the transistors Q₁₆₁ of the switching blocks S_(g12) and S_(g32) and the collector output of the transistor Q₁₆₂ of the switching block S_(g22).

To one input of the comparator CD₅₃ of the lower data comparator 193 is supplied the collector output of the transistor Q₁₆₁ of the switching block S_(g23) at the third column of the matrix circuit 180 and the collector output of the transistor Q₁₆₂ of the switching blocks S_(g13) and S_(g33), and to the other input is supplied the collector outputs of the transistors Q₁₆₁ of the switching blocks S_(g13) and S_(g33) and the collector output of the transistor Q₁₆₂ of the switching block S_(g23).

To one input of the comparator CD₅₄ of the lower data comparator 194 is supplied the collector output of the transistor Q₁₆₁ of the switching block S_(g24) at the fourth column of the matrix circuit 180 and the collector output of the transistor Q₁₆₂ of the switching blocks S_(g14) and S_(g34), and to the other input is supplied the collector outputs of the transistors Q₁₆₁ of the switching blocks S_(g14) and S_(g34) and the collector output of the transistor Q₁₆₂ of the switching block S_(g24).

To one input of the comparator CD₅₅ of the lower data comparator 195 is supplied the collector output of the transistor Q₁₆₁ of the switching block S_(g25) at the fifth column of the matrix circuit 180 and the collector output of the transistor Q₁₆₂ of the switching blocks S_(g15) and S_(g35), and to the other input is supplied the collector outputs of the transistors Q₁₆₁ of the switching blocks S_(g15) and S_(g35) and the collector output of the transistor Q₁₆₂ of the switching block S_(g25).

To one input of the comparator CD₅₆ of the lower data comparator 196 is supplied the collector output of the transistor Q₁₆₁ of the switching block S_(g26) at the sixth column of the matrix circuit 180 and the collector output of the transistor Q₁₆₂ of the switching blocks S_(g16) and S_(g36), and to the other input is supplied the collector outputs of the transistors Q₁₆₁ of the switching blocks S_(g16) and S_(g36) and the collector output of the transistor Q₁₆₂ of the switching block S_(g26).

To one input of the comparator CD₅₇ of the lower data comparator 197 is supplied the collector output of the transistor Q₁₆₁ of the switching block S_(g27) at the seventh column of the matrix circuit 180 and the collector output of the transistor Q₁₆₂ of the switching blocks S_(g17) and S_(g37), and to the other input is supplied the collector outputs of the transistors Q₁₆₁ of the switching blocks S_(g17) and S_(g37) and the collector output of the transistor Q₁₆₂ of the switching block S_(g27).

The output of the comparator CD₅₁ of the lower data comparator 191 is connected to the input of the output amplifier CA₅₁ , the positive output thereof is connected to both inputs of the 2-input AND gate AD₈₁, and the negative output is connected to one input of the 2-input AND gate AD₈₂ of the lower data comparator 192.

The output of the comparator CD₅₂ of the lower data comparator 192 is connected to the input of the output amplifier CA₅₂, the positive output thereof is connected to the other input of the 2-input AND gate AD₈₂, and the negative output is connected to one input of the 2-input AND gate AD₈₃ of the lower data comparator 193.

The output of the comparator CD₅₃ of the lower data comparator 193 is connected to the input of the output amplifier CA₅₃, the positive output thereof is connected to the other input of the 2-input AND gate AD₈₃, and the negative output is connected to one input of the 2-input AND gate AD₈₄ of the lower data comparator 194.

The output of the comparator CD₅₄ of the lower data comparator 194 is connected to the input of the output amplifier CA₅₄, the positive output thereof is connected to the other input of the 2-input AND gate AD₈₄, and the negative output is connected to one input of the 2-input AND gate AD₈₅ of the lower data comparator 195.

The output of the comparator CD₅₅ of the lower data comparator 195 is connected to the input of the output amplifier CA₅₅, the positive output thereof is connected to the other input of the 2-input AND gate AD₈₅, and the negative output is connected to one input of the 2-input AND gate AD₈₆ of the lower data comparator 196.

The output of the comparator CD₅₆ of the lower data comparator 196 is connected to the input of the output amplifier CA₅₆, the positive output thereof is connected to the other input of the 2-input AND gate AD₈₆, and the negative output is connected to one input of the 2-input AND gate AD₈₇ of the lower data comparator 197.

The output of the comparator CD₅₇ of the lower data comparator 197 is connected to the input of the output amplifier CA₅₇, the positive output thereof is connected to the other input of the 2-input AND gate AD₈₇, and the negative output is connected to the both inputs of the 2-input AND gate AD₈₈.

The outputs of the respective comparators CD₅₁ to CD₅₇ of the lower data comparators 191 to 197 constituted in this way become the level of "H" or "L" corresponding to the level of 2 inputs, and only one of the respective AND gates AD₈₁ to AD₈₈ outputs the "1" level.

The outputs of the AND gates AD₈₁ to AD₈₇ and AD₈₈ of the lower data comparators 191 to 197 are connected via the buffers B_(D1) to B_(D8), to the lower data encoder 185.

[0060]

The lower data encoder 185 is constituted by a data line LN₁₆₃ generating lower significant data BD₇₃ and BD₇₄ ; a selection line LN₁₆₄ generating the selection signal SEL₂₁ indicating that either of the outputs of the AND gates AD₈₁ to AD₈₄ of the lower data comparators 191 to 194 becomes "1"; and a selection line LN₁₆₅ generating the selection signal SEL₂₂ indicating that either of the outputs of the AND gates AD₈₅ to AD₈₇ and AD₈₈ of the lower data comparators 195 to 197 becomes "1".

FIG. 24 shows the correspondence between the outputs of the AND gates AU₄₁ to AU₄₃ on the upper data side and the outputs of the AND gates AD₈₁ to AD₈₈ on the lower data side, and the output conversion code data.

As mentioned above, in the matrix circuit 180 in the present embodiment, the respective switching blocks are divided to two in the row direction. At this division point C, as seen from FIG. 24, when paying attention to the upper significant 2 bits of the output conversion codes D₁ to D₄, division is made at the point at which the value of the upper significant 2 bits is switched.

Also, originally, it is necessary to make also the number of the upper data side AND gates (number of the upper data comparators) five, i.e., the same number in accordance with the number five of rows of the resistance columns, but in the present embodiment, two AND gates A_(L) and A_(H) corresponding to the resistance columns at the first row (lowermost stage) and the fifth row (uppermost stage) are omitted. As a result, two rows worth of the switching blocks which are to be arranged in the lowermost stage and uppermost stage are omitted.

An explanation will be made below of the reason why the AND gate and the switching block can be omitted using FIG. 24.

Here, at first, assume a structure in which a single row of the switching blocks is provided at the uppermost stage and, at the same time, corresponding to this, an upper data comparator having an AND gate A_(H) and a buffer for driving the upper data encoder 183 are provided.

In such a structure, when considering a case where the input analog signal V_(IN) is larger than the reference voltage V₁₁₂ (V_(IN) >V₁₁₂), the comparator output becomes "H" and the output of the AND gate A_(H) becomes the "1" level. The output of this case is one among four types of from [1111] to [1100] as shown in FIG. 24.

When paying attention to these four types of data, the data are similar to the data obtained where the output of the AND gate AU₄₁ of the upper data comparator 111 in one lower stage is at the "1" level and either of the outputs of the lower significant side AND gate AD₈₅ to AD₈₈ is at the "1" level.

Accordingly, where the AND gate A_(H) in the upper most stage becomes the "1" level, this means that it is sufficient if one lower stage of the switching blocks S_(g11) to S_(g17) and the buffer BU₄₁ are activated instead of activation of the switching block at the uppermost stage and the buffer for driving the upper data encoder 183.

This means that if the sum of the output of the AND gate A_(H) and the output of the AND gate AU₄₁ is given to the switching blocks S_(g11) to S_(g17) and the buffer BU₄₁, the switching block corresponding to the uppermost stage and the buffer for driving the upper data encoder become unnecessary.

Namely, in a case where V_(IN) >V₁₂₈ (=V₁₁₆), it is sufficient if the switching blocks S_(g11) to S_(g17) and the buffer BU₄₁ are activated as in the present embodiment, and it is not necessary to compare the input analog signal V_(IN) with the reference voltage V₁₁₂, and therefore also the upper data comparator corresponding to the uppermost stage becomes unnecessary.

Similarly, assume a structure in which a single row of the switching blocks is provided in the lower most stage, and the upper data comparator having the AND gate A_(L) is provided corresponding to this.

In such a structure, when considering a case where the input analog signal V_(IN) is smaller than the reference voltage V₁₂₄ (V_(IN) <V₁₂₄), the comparator output becomes "L" and the output of the AND gate A_(L) becomes the "1" level. The output of this case is one among four types of from [0011] to [0000] as shown in FIG. 24.

Paying attention to these four types of data, these data are similar to the data obtained in a case where the output of the AND gate AU₄₃ in one upper stage is at the "1" level and one of the outputs of the lower data side AND gates AD₈₁ to AD₈₄ is at the "1" level.

Accordingly, where the AND gate A_(L) in the lowermost stage becomes the "1" level, this means that it is sufficient if one upper stage of the switching blocks S_(g31) to S_(g37) and the buffer BU₄₃ are activated instead of activation of the switching block at the uppermost stage and the buffer for driving the upper data encoder 183.

This means that if the sum of the output of the AND gate A_(L) and the output of the AND gate AU₄₃ is given to the switching blocks S_(g31) to S_(g37) and the buffer BU₄₃, the switching block corresponding to the lowermost stage and the buffer for driving the upper data encoder become unnecessary.

Namely, in a case where V_(IN) <V₁₂₇ (=V₁₂₀), it is sufficient if the switching blocks S_(g31) to S_(g37) and the buffer BU₄₃ are activated as in the present embodiment, and it is not necessary to compare the input analog signal V_(IN) with the reference voltage V₁₂₄. Therefore, also the upper data comparator corresponding to the lowermost stage becomes unnecessary.

The selection gate 186 is constituted by AND gates A₅₁ to A₅₄, selects a single upper significant data from among the respective upper significant data of the L mode and R mode output from the upper data encoder 183 using the selection signals SEL₂₁ and SEL₂₂ output from the lower data encoder 185, and outputs the same via the OR-gates OR₄₁ and OR₄₂ as the conversion codes D₁ and D₂.

Concretely, one input terminal of the AND gate A₅₁ is connected to one line (upper data side) of the encoder line LN₁₆₁ generating the data for the L mode of the upper data encoder 183, and the other input terminal is connected to the selection line LN₁₆₄ outputting the selection signal SEL₂₁ of the lower data encoder 185.

One input terminal of the AND gate A₄₂ is connected to one line (upper significant side) of the encoder line LN₁₆₂ generating the data for the R mode of the upper data encoder 183, and the other input terminal is connected to the selection line LN₁₆₅ outputting the selection signal SEL₂₂ of the lower data encoder 185.

The outputs of these AND gates A₅₁ and A₅₂ are connected to the respective input terminals of the 2-input OR-gate OR₄₁.

One input terminal of the AND gate A₅₃ is connected to the other line (lower data side) of the encoder line LN₁₆₁ generating the data for the L mode of the upper data encoder 183, and the other input terminal is connected to the selection line LN₁₆₄ outputting the selection signal SEL₂₁ of the lower data encoder 185.

One input terminal of the AND gate A₅₄ is connected to the other line (lower significant side) of the encoder line LN₁₆₂ generating the data for the R mode of the upper data encoder 183, and the other input terminal is connected to the selection line LN₁₆₅ outputting the selection signal SEL₂₂ of the lower data encoder 185.

The outputs of these AND gates A₅₃ and A₅₄ are connected to the respective input terminals of the 2-input OR-gate OR₄₂.

The exclusive-OR gate EXO₄₁ obtains the exclusive-OR between the lower significant data BD₇₃ output from one line of the data line LN₁₆₃ of the lower data encoder 185 and the signal obtained by inverting the output level of the AND gate A_(U2) of the upper data comparator 182 by the inverter 184 and outputs the result thereof as the lower data conversion code D₃.

The exclusive-OR gate EXO₄₂ obtain the exclusive-OR between the lower significant data BD₇₄ output from the other line of the data line LN₁₆₃ of the lower data encoder 185 and the signal obtained by inverting the output level of the AND gate AU₄₂ of the upper data comparator 182 by the inverter 184 and outputs the result thereof as the lower data conversion code D₄.

Next, an explanation will be made of the operation by the above-described structure.

For example, when the sampling voltage V_(S) of the sampled analog signal is represented as V_(RB) <V_(S) <V₁₂₇, the outputs of the comparators CU₄₁ and CU₄₂ of the upper data comparators 181 and 182 become all "L", so that the digital signals are output, i.e. , "0" is output from the AND gates AU₄₁ to AU₄₂, and "1" is output from the AND gate AU₄₃, respectively.

As a result, a digital signal such as [001] is input to the upper data encoder 183. At the upper data encoder 183, using a so-called wired-OR circuit, [00] is generated in the two columns of encoder lines [LN₁₆₁ ] generating the L mode data; and [01] is generated in the two columns of encoder lines [LN₁₆₂ ] generating the R mode data; respectively, which are output to the selection gate 183.

Also, when the sampling voltage V_(S) is represented as V₁₂₇ <V_(S) <V₁₂₈, the output of the comparator CU₁ of the upper data comparator 181 becomes "L", and the output of the comparator CU₂ of the upper data comparator 182 becomes "H", so that the digital signals are output, i.e., "0" is output from the AND gates AU₄₁ to AU₄₃ of the upper data comparator 181, and "1" is output from the AND gate AU₄₂ of the upper data comparator 182, respectively.

As a result, a digital signal such as [010] is input to the upper data encoder 183. At the upper data encoder 183, using a so-called wired-OR circuit, [10] is generated in the two columns of encoder lines [LN₁₆₁ ] generating the L mode data; and [01] is generated in the two columns of encoder lines [LN₁₆₂ ] generating the R mode data; respectively, which are output to the selection gate 183.

Also, when the sampling voltage V_(S) is represented as V₁₂₈ <V_(S) <V_(RT), the output of the comparator CU₄₁ of the upper data comparator 181 becomes "H", and the output of the comparator CU₄₂ of the upper data comparator 182 becomes "L", so that the digital signals are output, i.e., "1" is output from the AND gate AU₄₁ of the upper data comparator 181, and "0" is output from the AND gates AU₄₂ and AU₄₃ of the upper data comparator 182, respectively.

As a result, a digital signal such as [100] is input to the upper data encoder 183. At the upper data encoder 183, using a so-called wired-OR circuit, [10] is generated in the two columns of encoder lines [LN₁₆₁ ] generating the L mode data; and [11] is generated in the two columns of encoder lines [LN₁₆₂ ] generating the R mode data; respectively, which are output to the selection gate 183.

In parallel with this, the transistors Q₁₆₃ of the respective switching blocks of the matrix circuit 180 connected to the control lines (x₄₁, x₄₂, and x₄₃) at which the digital output signal has become "1" among the respective AND gates AU.sub.(41, 42, 43) are controlled to turn ON in units of rows, and further a fine digitization of the quantization level is executed.

For example, when only the output of the AND gate AU₄₃ becomes the "1" level, the transistors Q₁₆₃ of the switching blocks S_(g31) to S_(g17) become ON, so that the reference voltages V₁₁₉ to V₁₂₅ divided by the reference resistors R₁₄₉ to R₁₅₆ and the sampling voltage V_(S) are differentially amplified at the switching blocks S_(g31) to S_(g37) and compared by the lower data comparators 191 to 197.

Similarly, when the output of the AND gate AU₄₂ is at the "1" level, the switching blocks S_(g21) to S_(g27) are activated, so that the differential amplification operation is performed, and the comparison by the lower data comparator 191 to 197 is carried out.

In this way, in the lower data conversion codes, the sampled voltage V_(S) and the reference voltage divided by the reference resistance of that row are compared in units of rows of the switching blocks, so that a digital signal in accordance with the results of comparison will be output from the AND gates AD₈₁ to AD₈₇ and AD₈₈ of the lower data comparators 191 to 197.

At this time, in a case where the input analog signal V_(IN) when converting the upper significant 2 bits D₁ and D₂ is defined as V_(IN) <V₁₂₇, and the analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as V_(IN) <V₁₂₂, or in a case where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₁₂₇ <V_(IN) <V₁₂₈, and the analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as V₁₁₈ <V_(IN), or in a case where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₁₂₈ <V_(IN), and the analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as V_(IN) <V₁₁₄, and the signal of "1" level is output from a single AND gate among the AND gates AD₈₁ to AD₈₄ of the lower data comparators 191 to 194 to the lower data encoder 185, in the lower data encoder 185, the selection line LN₁₆₄ becomes "1".

As a result, the selection signal SEL₂₁ is input to the selection gate 186 as the "1" level, and the selection signal SEL₂₂ is input to the selection gate 186 as the "0" level.

In the selection gate 186, along with the fact that only the selection signal SEL₂₁ is input as the "1" level, only the AND gates A₅₁ and A₅₃ are activated.

To these AND gates A₅₁ and A₅₃, the bit data of the upper data side and lower data side of the upper significant data for the L mode generated in the line LN₁₂₁ of the upper data encoder 183 are respectively supplied.

Accordingly, in the selection gate 186, the respective bits of the upper significant data at the L mode are selected, and as a result, they are output as the upper significant data conversion codes D₁ and D₂ via the OR gates OR₄₁ and OR₄₂.

Concretely, when the sampling voltage V_(S) of the analog signal V_(IN) is defined as V_(RB) <V_(S) <V₁₂₇, the upper data conversion codes [D₁, D₂ ] are output as [00]; when V₁₂₇ <V_(S) <V₁₂₈ stands, the upper significant data conversion codes [D₁, D₂ ] are output as [10]; and when V₁₂₈ <V_(S) <V_(RT) stands, the upper significant data conversion codes [D₁, D₂ ] are output as [10].

Also, in the lower data encoder 185, when the output of the AND gate AD₈₁ of the lower data comparator 191 is "1", the lower significant data BD₇₃ and BD₇₄ are generated as [11]; when the output of the AND gate AD₈₂ of the lower data comparator 192 is "1", the lower significant data BD₇₃ and BD₇₄ are generated as [10]; when the output of the AND gate AD₈₃ of the lower data comparator 193 is "1", the lower significant data BD₇₃ and BD₇₄ are generated as [01]; and when the output of the AND gate AD₈₄ of the lower data comparator 194 is "1", the lower significant data BD₇₃ and BD₇₄ are generated as [00], and the data BD₇₃ is output to the exclusive-OR gate EXO₄₁, and the data BD₇₄ is output to the exclusive-OR gate EXO₄₂.

In the exclusive-OR gates EXO₄₁ and EXO₄₂, when V_(RB) <V_(S) <V₁₂₇ and V₁₂₈ <V_(S) <V_(RT) stand, that is where the switching blocks S_(g31) to S_(g37) and S_(g11) to S_(g17) at the first row and third row from the bottom of the matrix circuit 180 are selected, since the direction of application of the reference voltage is the forward direction, the levels of the lower significant data are output as the lower significant data conversion codes D₃ and D₄ while inverting the output level of the lower data encoder 185.

Contrary to this, when V₁₂₇ <V_(S) <V₁₂₈ stands, that is where the switching blocks S_(g21) to S_(g27) at the second row from the bottom of the matrix circuit 180 are selected, since the direction of application of the reference voltage is the inverse direction, the levels of the lower significant data are held at the output level of the lower data encoder 185 level and output as the lower significant data conversion codes D₃ and D₄.

Also, in a case where the input analog signal V_(IN) when converting the upper significant 2 bits D₁ and D₂ is defined as V_(IN) <V₁₂₇, and the analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as V₁₂₂ <V_(IN), or in a case where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as ₁₂₇ <V_(IN) <V₁₂₈, and the analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as V_(IN) <V₁₁₈ ; or in a case where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₁₂₈ <V_(IN), and the analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as V₁₁₄ <V_(IN), and the signal of "1" level is output from a single AND gate among the AND gates AD₈₅ to AD₈₇ and AND gate AD₈₈ of the lower data comparators 195 to 197 to the lower data encoder 185, in the lower data encoder 185, the selection line LN₁₆₅ becomes "1".

As a result, the selection signal SEL₂₂ is input to the selection gate 186 as the "1" level, and the selection signal SEL₂₁ is input to the selection gate 186 as the "0" level.

In the selection gate 186, along with the fact that only the selection signal SEL₂₂ is input as the "1" level, only the AND gates A₅₂ and A₅₄ are activated.

To these AND gates A₅₂ and A₅₄, the bit data of the upper data side and lower data side of the upper significant data for the R mode generated in the line LN₁₆₂ of the upper data encoder 183 are respectively supplied.

Accordingly. in the selection gate 186, the respective bits of the upper significant data at the R mode are selected, and as a result, they are output as the upper significant data conversion codes D₁ and D₂ via the OR gates OR₄ 1 and OR₄₂.

Concretely, when the sampling voltage V_(S) of the analog signal V_(IN) is defined as V_(RB) <V_(S) <V₁₂₇, the upper data conversion codes [D₁, D₂ ] are output as [01]; when V₁₂₇ <V_(S) <V₁₂₈ stands, the upper significant data conversion codes [D₁, D₂ ] are output as [01]; and when V₁₂₈ <V_(S) <V_(RT) stands, the upper significant data conversion codes [D₁, D₂ ] are output as [11].

Also, in the lower data encoder 185, when the output of the AND gate AD₈₅ of the lower data comparator 195 is "1", the lower significant data BD₇₃ and BD₇₄ are generated as [11]; when the output of the AND gate AD₈₆ of the lower data comparator 196 is "1", the lower significant data BD₇₃ and BD₇₄ are generated as [10]; when the output of the AND gate AD₈₇ of the lower data comparator 197 is "1", the lower significant data BD₇₃ and BD₇₄ are generated as [01]; and when the output of the AND gate AD₈₈ is "1", the lower significant data BD₇₃ and BD₇₄ are generated as [00], and the data BD₇₃ is output to the exclusive-OR gate EXO₄₁, and the data BD₇₄ is output to the exclusive-OR gate EXO₄₂.

In the exclusive-OR gates EXO₄₁ and EXO₄₂, when V_(RB) <V_(S) <V₁₂₇ and V₁₂₈ <V_(S) <V_(RT) stand, that is where the switching blocks S_(g31) to S_(g37) and S_(g11) to S_(g17) of the first row and third row from the bottom of the matrix circuit 180 are selected, since the direction of application of the reference voltage is the forward direction, the levels of the lower significant data are output as the lower significant data conversion codes D₃ and D₄ while inverting the output level of the lower data encoder 185.

Contrary to this, when V₁₂₇ <V_(S) <V₁₂₈ stands, that is where the switching blocks S_(g21) to S_(g27) at the second row from the bottom of the matrix circuit 180 are selected. since the direction of application of the reference voltage is the inverse direction, the levels of the lower significant data are held at the output level of the lower data encoder 185 as they are and output as the lower significant data conversion codes D₃ and D₄.

As explained above, according to the present embodiment, the lower data codes are divided to two groups, signals SEL₂₁ and SEL₂₂ for selecting the L mode data and R mode data are output from the lower data encoder 185 obtaining this group of conversion codes, so that the L mode data and R mode data output from the upper data encoder 183 are selected, thereby obtaining the upper data conversion codes D₁ and D₂, and therefore it is possible to use the selection signal directly for the selection of the upper significant data without the use of the inverted gate and inhibit gate as in the conventional circuit.

Accordingly, the input of the selection signal to the selection gate 186 is not delayed relative to the output of the upper data encoder 183, and thus the increase of speed of conversion processing can be achieved.

Also, in addition to the fact that the inverted gate and inhibit gate become unnecessary, the number of selection signals can be reduced to two, and also the number of the upper data codes to be selected and the number of the input gates of the selection gate can be reduced to two.

Further, the upper data comparator 181 detecting the change of the data between the third row and second row acts also as the upper data comparator for the uppermost stage of the matrix circuit 180, and the upper data comparator 182 detecting the change of the data between the second row and first row acts also as the upper data comparator for the lowermost stage of the matrix circuit 180, and therefore the number of the upper data comparators and the number of rows of the switching blocks which conventionally had to be (2^(a) -1) and 2^(a), respectively can be reduced to (2^(a) -2) and (2^(a) -1) rows, respectively.

Accordingly, there is an advantage that an A/D converter circuit with which the reduction of the chip area and the reduction of the power consumption can be achieved can be realized.

An explanation will next be made of an eighth embodiment of the present invention.

FIGS. 25A-25C are circuit diagrams showing the eighth embodiment of the A/D converter circuit according to the present invention.

The point of difference of the present embodiment from the above-mentioned seventh embodiment resides in the constitution that the number of the selection lines of the lower data encoder 205 is reduced to only one line, i.e., LN₁₇₄, to generate only one selection signal SEL₃₁ from among the selection signals, and a signal obtained by inverting the level of the selection signal SEL₃₁ at the inverter 218 is supplied as the signal in place of the selection signal SEL₂₂ to the other inputs of the AND gates A₆₂ and A₆₄ of the selection gate 260.

According to the present eighth embodiment, in addition to the effect of the above-described seventh embodiment, a simpler structure can be realized, and the chip area can be further reduced.

Note that, in the above-mentioned first and second embodiments, an explanation was made taking as an example an A/D converter circuit for four bits, but needless to say the present invention can be applied to an A/D converter circuit for more bits as well.

Also, in the above-mentioned seventh and eighth embodiments, the structure in which the other output pin buffers are arranged on the input side of the upper data encoder and the lower data encoder was shown, but these other output pin buffers are provided so as to reliably drive the upper data encoder and the lower data encoder, and it is necessary to provide the same according to a certain capacitance of the upper data encoder and the lower data encoder acting as a so-called load.

As explained above, according to the present invention, there are advantages such that the inverted gate and inhibit gate which have been conventionally necessary become unnecessary, and the increase of speed of conversion processing can be achieved.

Also, in addition to the fact that the inverted gate and inhibit gate become unnecessary, the number of the selection signals can be reduced, the number of the upper significant codes to be selected and the number of the input gates of the selection gates can be reduced, and further the number of the upper data comparators and the number of switching block rows of the data change point detection circuit can be reduced, and therefore there is an advantage that a reduction of the chip area and a reduction of the power consumption can be achieved.

FIGS. 26A-26C are circuit diagrams showing a ninth embodiment of the A/D converter circuit according to the present invention.

In FIG. 26, 230 denotes a matrix circuit; 231 to 234 denote upper data comparators; 235, an upper data encoder; 241 to 247 denote lower data comparators; 236, a lower data encoder; 237, a selection gate; 238, an inverter; R₂₀₁ to R₂₁₆ denote reference resistance elements; BU₁₀₁ to BU₁₀₅, BD₁₀₁ and BD₁₀₇ denote multiple output pin buffers; OR₁₀₁ and OR₁₀₂ denote OR gates; and EXO₁₀₁ and EXO₁₀₂ denote exclusive-OR gates; respectively.

The matrix circuit 230 is constituted by the arrangement of 35 switching blocks S_(i11) to S_(i17), S_(i21) to S_(i27), S_(i31) to S_(i37), S_(i41) to S_(i47), and S_(i51) to S_(i57) in the form of a matrix comprising five rows and seven columns.

The respective switching blocks S_(i11) to S_(i17), S_(i21) to S_(i27), S_(i31) to S_(i37), S_(i41) to S_(i47), and S_(i51) to S_(i57) are constituted by differential type amplifiers comprising the npn-type transistors Q₂₀₁, Q₂₀₂, and Q₂₀₃.

Excluding the switching blocks S_(i11) to S_(i14) and S_(i54) to S_(i57), reference voltage obtained by dividing the reference voltages V_(RT) to V_(RB) by the reference resistance elements R₂₀₁ to R₂₁₆ are supplied to the base of one side transistors Q₂₀₁ constituting a so-called differential pair of the switching blocks, and analog signals V_(IN) to be converted to the digital code are supplied to the base of the other side transistors Q₂₀₂, respectively.

Also, the emitters of the transistors Q₂₀₁ and Q₂₀₂ are connected to each other, and the middle point of connection thereof is connected to the current source I via the transistor Q₂₀₃ switched by the control signals x₁₀₁ to x₁₀₅, respectively.

Also, to the collectors of the transistors Q₂₀₁ and Q₂₀₂, the power source voltage V_(DD) is supplied via the resistance element r, the output of which is input to the comparators CD₁₀₁ to CD₁₀₇ of the seven lower data comparators 241 to 247 as mentioned later, which act also as the initial stage amplifiers of the lower data comparators 241 to 247.

Also, the collectors of the transistors Q₁₀₁ and Q₁₀₂ of the switching block at the second row and the fourth row from the bottom of the diagram are connected to the line in an opposite direction to that for the collector output of the transistors Q₁₀₁ and Q₁₀₂ of the switching blocks of the first row and third row, and steps are taken so that the line of the serial reference resistance elements R₂₀₁ to R₂₁₆ to which the reference potential V_(RT) -V_(RB) is applied can be formed by folding-back.

The reference resistance elements R₂₀₁ to R₂₁₆ are serially connected between the two reference potentials V_(RT) and V_(RB) and arranged by folding-back so as to extend over each predetermined number of rows, e.g., five rows in the present embodiment, to correspond to the matrix arrangement of the switching blocks in the matrix circuit 230.

Concretely, each two resistance elements R₂₁₆ and R₂₁₅ and R₂₀₂ and R₂₀₁ are serially connected at the first row and the fifth row from the bottom in the diagram, and the resistance elements R₂₁₄ to R₂₁₁, R₂₁₀ to R₂₀₇, and R₂₁₆ to R₂₁₃ are serially connected at the second row to the fourth row, respectively.

Viewing this folding-back arrangement of the resistance element columns from the reference potential V_(RB) terminal side positioned on the left end and lower end side of the matrix circuit 180, the wiring pattern extended in the right direction in the diagram is folded-back between the switching block column of the fourth column from the left in the diagram and the switching block column of the fifth column, and two resistance elements R₂₁₆ and R₂₁₅ are connected in series corresponding to the arrangement position of the switching blocks S_(i54) and S_(i53) of the first row from the bottom, whereby the first row of resistance column is constituted.

The resistance column of the first row is folded-back between the switching block column of the third column and the switching block column of the second column, and four resistance elements R₂₁₄ to R₂₁₁ are connected in series between the switching block rows of the first row and the second row and corresponding to the arrangement position of the switching blocks S_(i43) to S_(i46) of the second row, whereby the resistance column of the second row is constituted.

The resistance column of the second row is folded-back between the switching block column of the fifth column and the switching block column of the sixth column, and four resistance elements R₂₁₀ to R₂₀₇ are connected in series between the switching block rows of the second row and the third row and corresponding to the arrangement position of the switching blocks S_(i36) to S_(i33) at the third row, whereby the resistance column of the third row is constituted.

The resistance column of the third row is folded-back between the switching block column of the third column and the switching block column of the second column, and four resistance elements R₂₀₆ to R₂₀₃ are connected in series between the switching block rows of the fourth row and the fifth row and corresponding to the arrangement position of the switching blocks S_(i23) to S_(i26) of the fourth row, whereby the resistance column of the fourth row is constituted.

The resistance column of the fourth row is folded-back between the switching block column of the fifth column and the switching block column of the sixth column, two resistance elements R₂₀₂ and R₂₀₁ are connected in series between the switching block rows at the fourth row and the fifth row and corresponding to the arrangement position of the switching blocks S_(i16) to S_(i15) at the fifth row, and one end of the resistance element R₂₀₁ is connected to the terminal of the reference potential V_(RT), whereby the resistance column of the fifth row is constituted.

Namely, the resistance columns at the first row and the fifth row are arranged with a deviation of a half cycle with respect to the resistance columns of the second row to the fourth row so that the position exhibiting the lowest value of the reference voltage (connection point between the reference potential V_(RB) terminal and the resistance element R₂₁₆) and the position exhibiting the highest value (connection point between the reference potential V_(RT) terminal and the resistance element R₁) are positioned at an intermediate point in the row direction of the switching blocks arranged in the form of the matrix.

Such an arrangement structure of resistance columns is made for the purpose of dividing the switching block columns comprising seven columns into two groups, i.e. the group comprising the switching block columns of from the first column to the fourth column and the group of the switching block columns of from the fifth column to the seventh column at the switching point between upper data and lower data as will be mentioned later.

Also, the voltages V₂₂₁ and V₂₂₄ generated between the rows of the respective resistance columns are supplied to the upper data comparators 231 to 234 as the reference voltages obtained by dividing the reference potentials V_(RT) to V_(RB) by rough quantization, respectively.

In the structure of FIG. 26, when assuming that the voltage between the reference potentials V_(RT) to V_(RB) is V_(REF), the respective reference voltages V₂₂₁ to V₂₂₄ become the following values, respectively:

    V.sub.221 =(14/16)·V.sub.REF

    V.sub.222 =(10/16)·V.sub.REF

    V.sub.223 =(6/16)·V.sub.REF

    V.sub.224 =(2/16)·V.sub.REF

Further, wiring is carried out so that the respective reference voltages V₂₀₁ to V₂₁₅ divided by the reference resistance elements R₂₀₁ to R₂₁₆ are supplied to the base of the transistor Q₂₀₁ of the predetermined switching block.

Concretely, a reference voltage V₂₀₁ [=(15/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₀₁ and R₂₀₂ is supplied to the bases of the transistors Q₂₀₁ of the switching blocks S_(i15) and S_(i27).

A reference voltage V₂₀₂ [=V₂₂₁ =(14/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₀₂ and R₂₀₃ is supplied to the bases of the transistors Q₂₀₁ of the switching blocks S_(i16) and S_(i26).

A reference voltage V₂₀₃ [=(13/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₀₃ and R₂₀₄ is supplied to the bases of the transistors Q₂₀₁ of the switching blocks S_(i17) and S_(i25).

A reference voltage V₂₀₄ [=(12/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₀₄ and R₂₀₅ is supplied to the base of the transistor Q₂₀₁ of the switching block S_(i24).

A reference voltage V₂₀₅ [=(11/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₀₅ and R₂₀₆ is supplied to the bases of the transistors Q₂₀₁ of the switching blocks S_(i23) and S_(i31).

A reference voltage V₂₀₆ [=V₂₂₂ =(10/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₀₆ and R₂₀₇ is supplied to the bases of the transistors Q₂₀₁ of the switching blocks S_(i22) and S_(i32).

A reference voltage V₂₀₇ [=(9/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₀₇ and R₂₀₈ is supplied to the bases of the transistors Q₂₀₁ of the switching blocks S_(i21) and S_(i33).

A reference voltage V₂₀₈ [=(8/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₀₈ and R₂₀₉ is supplied to the base of the transistor Q₂₀₁ of the switching block S_(i34).

A reference voltage V₂₀₉ [=(7/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₀₉ and R₂₁₀ is supplied to the bases of the transistors Q₂₀₁ of the switching blocks S_(i35) and S_(i47).

A reference voltage V₂₁₀ [=V₂₂₃ =(6/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₁₀ and R₂₁₁ is supplied to the bases of the transistors Q₂₀₁ of the switching blocks S_(i36) and S_(i46).

A reference voltage V₂₁₁ [=(5/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₁₁ and R₂₁₂ is supplied to the bases of the transistors Q₂₀₁ of the switching blocks S_(i37) and S_(i45).

A reference voltage V₂₁₂ [=(4/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₁₂ and R₂₁₃ is supplied to the base of the transistor Q₂₀₁ of the switching block S_(i44).

A reference voltage V₂₁₃ [=(3/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₁₃ and R₂₁₄ is supplied to the bases of the transistors Q₂₀₁ of the switching blocks S_(i43) and S_(i51).

A reference voltage V₂₁₄ [=V₂₂₄ =(2/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₁₄ and R₂₁₅ is supplied to the bases of the transistors Q₂₀₁ of the switching blocks S_(i42) and S_(i52).

A reference voltage V₂₁₅ [=(1/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₁₅ and R₂₁₆ is supplied to the bases of the transistors Q₂₀₁ of the switching blocks S_(i41) and S_(i53).

Upper data comparators 231, 232, 233 and 234 respectively are provided with comparators CU₁₀₁ to CU₁₀₄, complementary-type output amplifiers CA₁₀₁ to CA₁₀₅, and AND gates AU₁₀₁ to AU₁₀₄.

An analog signal V_(IN) is supplied to one input of the comparator CU₁₀₁ of the upper data comparator 231, and a reference voltage V₂₂₁ [=(14/16)·V_(REF) ] obtained by dividing the reference potentials V_(RT) to V_(RB) by rough quantization is supplied to the other input.

The analog signal V_(IN) is supplied to one input of the comparator CU₁₀₂ of the upper data comparator 232, and a reference voltage V₂₂₂ [=(10/16)·V_(REF) ] obtained by dividing the reference potentials V_(RT) to V_(RB) by rough quantization is supplied to the other input.

The analog signal V_(IN) is supplied to one input of the comparator CU₁₀₃ of the upper data comparator 233, and a reference voltage V₂₂₃ [=(6/16)·V_(REF) ] obtained by dividing the reference potentials V_(RT) to V_(RB) by rough quantization is supplied to the other input.

The analog signal V_(IN) is supplied to one input of the comparator CU₁₀₄ of the upper data comparator 234, and a reference voltage V₂₂₄ [=(2/16)·V_(REF) ] obtained by dividing the reference potentials V_(RT) to V_(RB) by rough quantization is supplied to the other input.

The output of comparator CU₁₀₁ of the upper data comparator 231 is connected to the input of the output amplifier CA₁₀₈, the positive output thereof is connected to both inputs of a 2-input AND gate AU₁₀₁, and the negative output is connected to one input of the 2-input AND gate AU₁₀₂ of the upper data comparator 232.

The output of comparator CU₁₀₂ of the upper data comparator 232 is connected to the input of the output amplifier CA₁₀₉, the positive output thereof is connected to the other input of the 2-input AND gate AU₁₀₂, and the negative output is connected to one input of the 2-input AND gate AU₁₀₃ of the upper data comparator 233.

The output of comparator CU₁₀₃ of the upper data comparator 233 is connected to the input of the output amplifier CA₁₁₀, the positive output thereof is connected to the other input of a 2-input AND gate AU₁₀₃, and the negative output is connected to one input of the 2-input AND gate AU₁₀₄ of the upper data comparator 234.

The output of comparator CU₁₀₄ of the upper data comparator 234 is connected to the input of the output amplifier CA₁₁₁, the positive output thereof is connected to the other input of a 2-input AND gate AU₁₀₄, and the negative output is connected to the two inputs of the 2-input AND gate AU₁₀₅.

The outputs of the respective comparators CU₁₀₁ to CU₁₀₄ of the upper data comparators 231 to 234 constituted in this way become the level of "H" or "L" corresponding to the level of the sampled analog signal V_(In), and only one among the respective AND gates AU₁₀₁ to AU₁₀₄ outputs the "1" level.

The output of the AND gate AU₁₀₁ of the upper data comparator 231 is connected via the buffer BU₁₀₁ to the upper data encoder 235 and, at the same time, connected to the bases of the transistors Q₂₀₃ of the switching blocks S_(i11) to S_(i17) and connected to the input of the inverter 238 via the buffer.

The AND gate AU₁₀₂ of the upper data comparator 232 is connected via the buffer BU₁₀₂ to the upper data encoder 235 and, at the same time, connected to the bases of the transistors Q₂₀₃ of the switching blocks S_(i21) to S₁₂₇.

The output of the AND gate AU₁₀₃ of the upper data comparator 233 is connected via the buffer BU₁₀₃ to the upper data encoder 235 and, at the same time, connected to the bases of the transistors Q₂₀₃ of the switching blocks S_(i31) to S_(i37) and connected to the input of the inverter 238 via the buffer.

The AND gate AU₁₀₄ of the upper data comparator 234 is connected via the buffer BU₁₀₄ to the upper data encoder 235 and, at the same time, connected to the bases of the transistors Q₂₀₃ of the switching blocks S_(i41) to S_(i47).

The output of the AND gate AU₁₀₅ is connected to the input of the buffer BU₁₀₅ and, at the same time, connected to the bases of the transistors Q₂₀₃ of the switching blocks S_(i51) to S_(i57) and connected to the input of the inverter 238 via the buffer.

The upper data encoder 235 is constituted by an encoder line LN₂₀₁ generating the data for an L (left) mode, and an encoder line LN₂₀₂ generating the data for an R (right) mode.

Namely, in the upper data encoder 235, respective encoder lines LN₂₀₁ and LN₂₀₂ are set corresponding to a first group of from the first column to the fourth column arranged on the left side from the center of the matrix circuit 230 and a second group of from the fifth column to the seventh column arranged on the right side among the switching blocks S_(i11) to S_(i17), S_(i21) to S_(i27), S_(i31) to S_(i37), S_(i41) to S_(i47) and S_(i51) to S_(i57) arranged in the matrix circuit 230. The data for the bits excluding the least significant bit (lower data side bit of the upper significant bits) among the upper significant 2 bits, in the case of the present embodiment, for the most significant bit (upper data side bit of the upper significant bits) among the upper significant 2 bits are set.

FIG. 27 shows the correspondence between the outputs of the respective AND gates AU₁₀₁, AU₁₀₂, AU₁₀₃, AU₁₀₄, and AU₁₀₅ of the upper data comparators 231 to 234 and the set output data code pattern of the respective encoder lines LN₂₀₁ and LN₂₀₂ of the upper data encoder 235.

The setting of data is carried out as shown in FIG. 28 in accordance with the most significant bit in the output data of the left side column group (corresponding to the L mode) and the right side column group (corresponding to the R mode) when dividing the same to two groups around the intermediate point C.

The lower data comparators 241 to 247 respectively are provided with comparators CD₁₀₁ to CD₁₀₇, complementary-type output amplifiers CA₁₀₁ to 107, and AND gates AD₁₀₁ to AD₁₀₇.

To one input of the comparator CD₁₀₁ of the lower data comparator 241 is supplied the collector outputs of the transistors Q₂₀₁ of the switching block S_(i11), S_(i31), and S_(i51) at the first column of the matrix circuit 230 and the collector outputs of the transistors Q₂₀₂ of the switching blocks S_(i21) and S_(i41), and to the other input is supplied the collector outputs of the transistors Q₂₀₁ of the switching blocks S_(i21) and S_(i41) and the collector outputs of the transistors Q₂₀₂ of the switching blocks S_(i11), S_(i31), and S_(i51).

To one input of the comparator CD₁₀₂ of the lower data comparator 242 is supplied the collector outputs of the transistors Q₂₀₁ of the switching block S_(i12), S_(i32), and S_(i52) at the second column of the matrix circuit 230 and the collector outputs of the transistors Q₂₀₂ of the switching blocks S_(i22) and S_(i42), and to the other input is supplied the collector outputs of the transistors Q₂₀₁ of the switching blocks S_(i22) and S_(i42) and the collector outputs of the transistors Q₂₀₂ of the switching blocks S_(i12), S_(i32), and S_(i52).

To one input of the comparator CD₁₀₃ of the lower data comparator 243 is supplied the collector outputs of the transistors Q₂₀₁ of the switching block S_(i13), S_(i33), and S_(i53) at the third column of the matrix circuit 230 and the collector outputs of the transistors Q₂₀₂ of the switching blocks S_(i23) and S_(i43), and to the other input is supplied the collector outputs of the transistors Q₂₀₁ of the switching blocks S_(i23) and S_(i43) and the collector outputs of the transistors Q₂₀₂ of the switching blocks S_(i13), S_(i33), and S_(i53).

To one input of the comparator CD₁₀₄ of the lower data comparator 244 is supplied the collector outputs of the transistors Q₂₀₁ of the switching block S_(i14), S_(i34), and S_(i54) at the fourth column of the matrix circuit 230 and the collector outputs of the transistors Q₂₀₂ of the switching blocks S_(i24) and S_(i44), and to the other input is supplied the collector outputs of the transistors Q₂₀₁ of the switching blocks S_(i24) and S_(i44) and the collector outputs of the transistors Q₂₀₂ of the switching blocks S_(i14), S_(i34), and S_(i54).

To one input of the comparator CD₁₀₅ of the lower data comparator 245 is supplied the collector outputs of the transistors Q₂₀₁ of the switching block S_(i15), S_(i35), and S_(i55) at the fifth column of the matrix circuit 230 and the collector outputs of the transistors Q₂₀₂ of the switching blocks S_(i25) and S_(i45), and to the other input is supplied the collector outputs of the transistors Q₂₀₁ of the switching blocks S_(i25) and S_(i45) and the collector outputs of the transistors Q₂₀₂ of the switching blocks S_(i15), S_(i35), and S_(i55).

To one input of the comparator CD₁₀₆ of the lower data comparator 246 is supplied the collector outputs of the transistors Q₂₀₁ of the switching block S_(i16), S_(i36), and S_(i56) at the sixth column of the matrix circuit 230 and the collector outputs of the transistors Q₂₀₂ of the switching blocks S_(i26) and S_(i46), and to the other input is supplied the collector outputs of the transistors Q₂₀₁ of the switching blocks S_(i26) and S_(i46) and the collector outputs of the transistors Q₂₀₂ of the switching blocks S_(i16), S_(i36), and S_(i56).

To one input of the comparator CD₁₀₇ of the lower data comparator 247 is supplied the collector outputs of the transistors Q₂₀₁ of the switching block S_(i17), S_(i37), and S_(i57) at the seventh column of the matrix circuit 230 and the collector outputs of the transistors Q₂₀₂ of the switching blocks S_(i27) and S_(i47), and to the other input is supplied the collector outputs of the transistors Q₂₀₁ of the switching blocks S_(i27) and S_(i47) and the collector outputs of the transistors Q₂₀₂ of the switching blocks S_(i17), S_(i37), and S_(i57).

The output of the comparator CD₁₀₁ of the lower data comparator 241 is connected to the input of the output amplifier CA₁₀₁, the positive output thereof is connected to both inputs of the 2-input AND gate AD₁₀₁, and the negative output is connected to one input of the 2-input AND gate AD₁₀₂ of the lower data comparator 242.

The output of the comparator CD₁₀₂ of the lower data comparator 242 is connected to the input of the output amplifier CA₁₀₂, the positive output thereof is connected to the other input of the 2-input AND gate AD₁₀₂, and the negative output is connected to one input of the 2-input AND gate AD₁₀₃ of the lower data comparator 243.

The output of the comparator CD₁₀₃ of the lower data comparator 243 is connected to the input of the output amplifier CA₁₀₃, the positive output thereof is connected to the other input of the 2-input AND gate AD₁₀₃, and the negative output is connected to one input of the 2-input AND gate AD₁₀₄ of the lower data comparator 244.

The output of the comparator CD₁₀₄ of the lower data comparator 244 is connected to the input of the output amplifier CA₁₀₄, the positive output thereof is connected to the other input of the 2-input AND gate AD₁₀₄, and the negative output is connected to one input of the 2-input AND gate AD₁₀₅ of the lower data comparator 245.

The output of the comparator CD₁₀₅ of the lower data comparator 245 is connected to the input of the output amplifier CA₁₀₅, the positive output thereof is connected to the other input of the 2-input AND gate AD₁₀₅, and the negative output is connected to one input of the 2-input AND gate AD₁₀₆ of the lower data comparator 246.

The output of the comparator CD₁₀₆ of the lower data comparator 246 is connected to the input of the output amplifier CA₁₀₆, the positive output thereof is connected to the other input of the 2-input AND gate AD₁₀₆, and the negative output is connected to one input of the 2-input AND gate AD₁₀₇ of the lower data comparator 247.

The output of the comparator CD₁₀₇ of the lower data comparator 247 is connected to the input of the output amplifier CA₁₀₇, the positive output thereof is connected to the other input of the 2-input AND gate AD₁₀₇, and the negative output is connected to both inputs of the 2-input AND gate AD₁₀₈.

The outputs of the respective comparators CD₁₀₁ to CD₁₀₇ of the lower data comparators 241 to 247 constituted in this way become the level of the two inputs, and only one among the respective AND gates AD₁₀₁ to AD₁₀₈ outputs the "1" level.

The output of the AND gates AD₁₀₁ to AD₁₀₇ and AD₁₀₈ of the lower data comparator 241 to 247 are connected via the buffers BD₁₀₁ to BD₁₀₈ to the lower data encoder 236.

The lower data encoder 236 is comprised of a data line LN₂₀₃ generating the lower significant data BD₁₁₃, and DB₁₁₄, a selection line LN₂₀₄ generating a selection signal SEL₁₀₁ indicating that one of the outputs of the AND gates AD₁₀₁ and AD₁₀₄ of the lower data comparators 241 to 244 becomes "1"; and a selection line LN₂₀₅ generating the selection signal SEL₁₀₂ indicating that one of the outputs of the AND gates AD₁₀₅ to AD₁₀₇ and AD₁₀₈ of the lower data comparators 245 to 247 becomes "1".

The selection signal SEL₁₀₁ is set for selecting the upper significant data of the L mode mentioned above, and the selection signal SEL₁₀₂ is set for selecting the upper significant data of the R mode.

FIG. 28 shows the correspondence between the outputs of the upper data side AND gates AU₁₀₁ to AU₁₀₅ and the lower data side AND gates AD₁₀₁ to AD₁₀₈ and the output conversion code data.

As mentioned above, in the matrix circuit 230 in the present embodiment, the switching blocks are divided into two in the row direction, and at this division point C, as seen from FIG. 28, when paying attention to the upper significant 2 bits of the output conversion codes D₁ to D₄, division is made at the point at which the value of the upper significant 2 bits is switched.

Further, the lower data encoder 236 outputs the selection signal SEL₁₀₂ as the conversion code D₂ on the lower data side (least significant bit of the upper significant bits) of the upper significant data excluded from the set data of the upper data encoder 235 based on a fact that, when paying attention to the upper significant 2 bits of the output conversion codes D₁ to D₄, there is a relationship of inversion of the level in the lower data side bits thereof between the L (left) side and the R (right side) around the intermediate point C.

The selection gate 237 is constituted by AND gates AD₁₀₁ and AD₁₀₂, selects a single upper significant data (the most significant bit among the upper significant bits) from among the respective upper significant data of the L mode and the R mode output from the upper data encoder 235 using the selection signals SEL₁₀₁ to SEL₁₀₂ output from the lower data encoder 236, and outputs the same as the conversion code D₁ via the OR gate OR₁₀₁.

[0065]

Concretely, one input terminal of the AND gate A₁₀₁ is connected to the encoder line LN₂₀₁ generating the data for the L mode of the upper data encoder 235, and the other input terminal is connected to the selection line LN₂₀₄ outputting the selection signal SEL₁₀₁ of the lower data encoder 236.

One input terminal of the AND gate A₁₀₂ is connected to the encoder line LN₂₀₂ generating the data for the R mode of the upper data encoder 235, and the other input terminal is connected to the selection line LN₂₀₅ outputting the selection signal SEL₁₀₂ of the lower data encoder 236.

The outputs of these AND gates A₁₀₁ and A₁₀₂ are connected to respective input terminals of the 2-input OR gate OR₁₀₁.

The exclusive-OR gate EXO₁₀₁ obtains the exclusive-OR between the lower significant data BD₁₁₃ output from one line of the data line LN₂₀₃ of the lower data encoder 236 and the signal obtained by inverting the sum of the output levels of the AND Gates AU₁₀₁, AU₁₀₃, or AU₁₀₅ of the upper data comparators 231 and 233 by the inverter 238 and outputs the result thereof as the lower significant data conversion code D₃.

The exclusive-OR gate EXO₁₀₂ obtains the exclusive-OR between the lower significant data BD₁₁₄ output from one line of the data line LN₂₀₃ of the lower data encoder 236 and the signal obtained by inverting the sum of the output levels of the AND gates AU₁₀₁, AU₁₀₃, or AU₁₀₅ of the upper data comparators 231 and 233 by the inverter 238 and outputs the result thereof as the lower significant data conversion code D₄.

Next, an explanation will be made of the operation by the above-described structure.

For example, when the sampling voltage V_(S) of the sampled analog signal is represented as V_(RB) <V_(S) <V₂₂₄, the outputs of the comparators CU₁₀₁ to CU₁₀₄ of the upper data comparators 231 to 234 become all "L", so that the digital signals are output, i. e., "0" is output from the AND gates AU₁₀₁ to AU₁₀₄, and "1" is output from the AU₁₀₅, respectively.

As a result, a digital signal such as [0000] is input to the upper data encoder 235. At the upper data encoder 235, using a so-called wired-OR circuit, the upper significant data of [0] are respectively generated in the encoder line [LN₂₀₁ ] generating the L mode data and the encoder line [LN₂₀₂ ] generating the R mode data, which are output to the selection gate 235.

Also, when the sampling voltage V_(S) of the sampled analog signal is represented as V₂₂₄ <V_(S) <V₂₂₃, the outputs of the comparators CU₁₀₁ to CU₁₀₃ of the upper data comparators 231 to 233 become all "H", so that the digital signals are output i.e., "0" is output from the AND gates AU₁₀₁ to AU₁₀₃ and AU₁₀₅ of the upper data comparators 231 to 233, and "1" is output from the AU₁₀₄ of the upper data comparator 234, respectively.

As a result, a digital signal such as [0001] is input to the upper data encoder 235. At the upper data encoder 235, using a so-called wired-OR circuit, the upper significant data of [0] is generated in the encoder line [LN₂₀₁ ] generating the L mode data, and the upper significant data of [0] is generated in the encoder line [LN₂₀₂ ] generating the R mode data, respectively, which are output to the selection gate 235.

Also, when the sampling voltage V_(S) is represented as V₂₂₃ <V_(S) <V₂₂₂, similarly the digital signals are output, i.e., "0" is output from the upper significant side AND gates AU₁₀₁, AU₁₀₂, AU₁₀₄, and AU₁₀₅, and "1" is output from the AND gate AU₁₀₃, respectively.

As a result, a digital signal such as [0010] is input to the upper data encoder 235, and the upper significant data are output, i.e.m [1] is output from the line [LN₂₀₁ ], and [0] is output from the line [LN₂₀₂ ], to the selection gate 235.

Further, when the sampling voltage V_(S) is represented as V₂₂₂ <V_(S) <V₂₂₁, similarly the digital signals are output, i.e., "0" is output from the upper significant side AND gates AU₁₀₁, AU₁₀₃, AU₁₀₄, and AU₁₀₅, and "1" is output from the AND gate AU₁₀₂, respectively.

As a result, a digital signal such as [0100] is input to the upper data encoder 235, and the upper significant data are output, i.e. [1] is output from the line [LN₂₀₁ ], and [1] is output from the line [LN₂₀₂ ], to the selection gate 235.

Similarly, when the sampling voltage V_(S) is represented as V₂₂₁ <V_(S) <V_(RT), the digital signals are output, i.e., "0" is output from the upper significant side AND gates AU₁₀₂, AU₁₀₃, AU₁₀₄, and AU₁₀₅, and "1" is output from the AND gate AU₁₀₁, respectively.

As a result, a digital signal such as [1000] is input to the upper data encoder 235, and the upper significant data are output, i.e., [1] is output from the line [LN₂₀₁ ], and [1] is output from the line [LN₂₀₂ ], to the selection gate 235.

In parallel with this, the transistors Q₂₀₃ of the respective switching blocks of the matrix circuit 230 connected to the control lines (x₁₀₁, x₁₀₂, x₁₀₃, x₁₀₄, and x₁₀₅) at which the digital output signal has become "1" among the respective AND gates AU.sub.(101, 102, 103, 104, 105) are controlled to turn ON in units of rows, and further a fine digitization of the quantization level is executed.

For example, when only the output of the AND gate AU₁₀₃ becomes the "1" level, the transistors Q₂₀₃ of the switching blocks S_(i31) to S_(i37) become ON, so that the reference voltages V₂₀₅ to V₂₁₁ divided by the reference resistors R₂₀₆ to R₂₁₁ and the sampling voltage V_(S) are differentially amplified at the switching blocks S_(i33) to S_(i36), and compared by the lower data comparators 241 to 247.

Similarly, when the output of the AND gate AU₁₀₂ is at the "1" level, the switching blocks S_(i21) to S_(i27) are activated, so that a differential amplification operation is performed, and the comparison by the lower data comparators 241 to 247 is carried out.

In this way, in the lower data conversion codes, the sampled voltage V_(S) and the reference voltage divided by the reference resistance of that row are compared in units of rows of the switching blocks, so that the digital signal in accordance with the result of comparison will be output from the AND gates AD₁₀₁ to AD₁₀₇ and AD₁₀₈ of the lower data comparators 241 to 247.

At this time, where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₂₄ >V_(IN), and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as V_(RB) <V_(IN) <[(V₂₂₄ +V₂₂₃)/2]; or where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₂₄ <V_(IN) <V₂₂₃, and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as V_(RB) <V_(IN) <[(V₂₂₄ +V₂₂₃)/2]; or where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₂₃ <V_(IN) <V₂₂₂, and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as [(V₂₂₃ +V₂₂₂)/2]<V_(IN) <[(V₂₂₁ +V₂₂₂)/2]; or where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₂₂ <V_(IN) <V₂₂₁, and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as [(V₂₂₃ +V₂₂₂)/2]<V_(IN) <[(V₂₂₁ +V₂₂₂)/2], in the lower data encoder 236, only the selection line LN₂₀₄ becomes "1". As a result, the selection signal SEL₁₀₁ is input to the selection gate 237 as the "1" level, and the selection signal SEL₁₀₂ is input to the selection gate 237 as the "0" level.

In the selection gate 237, along with the fact that only the selection signal SEL₁₀₁ is input as the "1" level, only the AND gate A₁₀₁ is activated.

To the AND gate A₁₀₁, the upper data side bit data of the upper significant data for the L mode generated in the line LN₂₀₁ of the upper data encoder 235 is supplied.

Accordingly, in the selection gate 237, the bits of the upper significant data at the L mode are selected, and as a result, they are output as the upper significant data conversion code D₁ via the OR gate OR₁₀₁.

At this time, in parallel with the output of the upper data conversion code D₁, the selection signal SEL₁₀₂ is output as the upper significant data conversion code D₂ while holding its level "0" as it is.

Concretely, when the sampling voltage V_(S) of the analog signal V_(IN) is defined as V_(RB) <V_(S) <V₂₂₄, the upper data conversion code [D₁, D₂ ] is output as [00]; when V₂₂₄ <V_(S) <V₂₂₃ stands, the upper data conversion code [D₁, D₂ ] is output as [00]; when V₂₂₃ <V_(S) <V₂₂₂ stands, the upper data conversion code [D₁, D₂ ] is output as [10]; and when V₂₂₂ <V_(S) <V₂₂₁ stands, the upper data conversion code [D₁, D₂ ] is output as [10].

Note that, when V₂₂₁ <V_(S) <V_(RT), the upper significant data conversion code [D₁, D₂ ] outputs [11], but this code will not be selected.

Also, in the lower data encoder 236, when the output of the AND gate AD₁₀₁ of the lower data comparator 241 is "1", the lower significant data BD₁₁₃ and BD₁₁₄ are generated as [11]; when the output of the AND gate AD₁₀₂ of the lower data comparator 242 is "1", the lower significant data BD₁₁₃ and BD₁₁₄ are generated as [10]; when the output of the AND gate AD₁₀₃ of the lower data comparator 243 is "1", the lower significant data BD₁₁₃ and BD₁₁₄ are generated as [01]; and when the output of the AND gate AD₁₀₄ of the lower data comparator 244 is "1", the lower significant data BD₁₁₃ and BD₁₁₄ are generated as [00], the data BD₁₁₃ is output to the exclusive-OR gate EXO₁₀₁, and the data BD₁₁₄ is output to the exclusive-OR gate EXO.sub. 102.

In the exclusive-OR gates EXO₁₀₁ and EXO₁₀₂, when V₂₂₄ <V_(S) <V₂₂₃ and V₂₂₂ <V_(S) <V₂₂₁ stand, that is where the switching blocks S_(i41) to S_(i47) and S_(i21) to S_(i27) at the second row and fourth row from the bottom of the matrix circuit 230 are selected, since the direction of application of the reference voltage is the forward direction, the levels of the lower significant data are output as the lower significant data conversion codes D₃ and D₄ while inverting the output level of the lower data encoder 236.

Contrary to this, when V_(RB) <V_(S) <V₂₂₄, V₂₂₃ <V_(S) <V₂₂₂ and V₂₂₁ <V_(S) <V_(RT) stand, that is where the switching blocks S_(i51) to S_(i57), S_(i31) to S_(i37) and S_(i11) to S_(i17) at the first row, third row, and fifth row from the bottom of the matrix circuit 230 are selected, since the direction of application of the reference voltage is the inverse direction, the levels of the lower significant data are held at the output level of the lower data encoder 236 as they are and output as the lower significant data conversion codes D₃ and D₄.

Also, where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₂₄ <V_(IN) <V₂₂₃, and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as [(V₂₂₄ +V₂₂₃)/2]<V_(IN) <[(V₂₂₃ +V₂₂₂)/2]; or where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₂₃ <V_(IN) <V₂₂₂, and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as [(V₂₂₄ +V₂₂₃)/2]<V_(IN) <[(V₂₂₃ +V₂₂₂)/2]; or where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₂₂ <V_(IN) <V₂₂₁, and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as [(V₂₂₂ +V₂₂₁)/2]<V_(IN) <V_(RT) ; or where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₂₁ <V_(IN), and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as [(V₂₂₂ +V₂₂₁)/2]<V_(IN) <V_(RT), in the lower data encoder 236, only the selection line LN₂₀₅ becomes "1".

As a result, the selection signal SEL₁₀₂ is input to the selection gate 237 as the "1" level, and the selection signal SEL₁₀₁ is input to the selection gate 237 as the "0" level.

In the selection gate 237, along with the fact that only the selection signal SEL₁₀₂ is input as the "1" level, only the AND gate A₁₀₂ is activated.

To the AND gate A₁₀₂, the upper data side bit data of the upper significant data for the R mode generated in the line LN₂₀₂ of the upper data encoder 235 is supplied.

Accordingly, in the selection gate 237, the bits of the upper significant data at the R mode are selected, and as a result, they are output as the upper significant data conversion code D₁ via the OR gate OR₁₀₁.

At this time, in parallel with the output of the upper data conversion code D₁, the selection signal SEL₁₀₂ is output as the upper significant data conversion code D₂ while holding its level "1" as it is.

Concretely, when the sampling voltage V_(S) of the analog signal V_(IN) is defined as V₂₂₄ <V_(S) <V₂₂₃, the upper data conversion code [D₁, D₂ ] is output as [01]; when V₂₂₃ <V_(S) <V₂₂₂ stands, the upper data conversion code [D₁, D₂ ] is output as [01]; when V₂₂₂ <V_(S) <V₂₂₁ stands, the upper data conversion code [D₁, D₂ ] is output as [11]; and when V₂₂₁ <V_(S) <V_(RT) stands, the upper data conversion code [D₁, D₂ ] is output as [11].

Note that, when the sampling voltage V_(S) is defined as V_(RB) <V_(S) <V₂₂₄, the upper significant data conversion code [D₁, D₂ ] outputs [00], but this code will not be selected.

Also, in the lower data encoder 236, when the output of the AND gate AD₁₀₅ of the lower data comparator 245 is "1", the lower significant data BD₁₁₃ and BD₁₁₄ are generated as [11]; when the output of the AND gate AD₁₀₆ of the lower data comparator 246 is "1", the lower significant data BD₁₁₃ and BD₁₁₄ are generated as [10]; when the output of the AND gate AD₁₀₇ of the lower data comparator 247 is "1", the lower significant data BD₁₁₃ and BD₁₁₄ are generated as [01]; and when the output of the AND gate AD₁₀₈ is "1", the lower significant data BD₁₁₃ and BD₁₁₄ are generated as [00], the data BD₁₁₃ is output to the exclusive-OR gate EXO₁₀₁, and the data BD₁₁₄ is output to the exclusive-OR gate EXO₁₀₂.

In the exclusive-OR gates EXO₁₀₁ and EXO₁₀₂, when V₂₂₄ <V_(S) <V₂₂₃ and V₂₂₂ <V_(S) <V₂₂₁ stand, that is where the switching blocks S_(i41) to S_(i47) and S_(i21) to S_(i27) at the second row and fourth row from the bottom of the matrix circuit 230 are selected, since the direction of application of the reference voltage is the forward direction, the levels of the lower significant data are output as the lower significant data conversion codes D₃ and D₄ while inverting the output level of the lower data encoder 236.

Contrary to this, when V_(RB) <V_(S) <V₂₂₄, V₂₂₃ <V_(S) <V₂₂₂ and V₂₂₁ <V_(S) <V_(RT) stand, that is where the switching blocks S_(i51) to S_(i57), S_(i31) to S_(i37) and S_(i11) to S_(i17) at the first row, third row, and fifth row from the bottom of the matrix circuit 230 are selected, since the direction of application of the reference voltage is the inverse direction, the levels of the lower significant data are held at the output level of the lower data encoder 236 as they are and output as the lower significant data conversion codes D₃ and D₄.

As explained above, according to the present embodiment, the lower significant codes are divided to two groups, signals SEL₁₀₁ and SEL₁₀₂ for selecting the L mode data and R mode data are output from the lower data encoder 236 obtaining the conversion code of the groups, and the L mode data and R mode data output from the upper data encoder 235 are selected, to obtain the upper significant data conversion code D₁, and output the selection signal SEL₁₀₁ and the selection signal SEL₁₀₂ inverted in its level as the lower significant side conversion code D₂ of the upper significant bit data. Therefore the selection signal can be used directly for the selection of the upper significant data without the use of the inverted gate and inhibit gate as in the conventional circuit.

Accordingly, the input of the selection signal to the selection gate 237 is not delayed relative to the output of the upper data encoder 235, and thus the increase of speed of conversion processing can be achieved.

Also, in addition to the fact that the inverted gate and inhibit gate become unnecessary, the number of the selection signals can be reduced to two, and also the number of the upper data codes to be selected and the number of the input gates of selection gates can be reduced to two. Therefore an A/D converter circuit with which the reduction of the chip area and the reduction of the power consumption can be achieved can be realized.

FIGS. 29A-29C are circuit diagrams showing a 10th embodiment of the A/D converter circuit according to the present invention.

The point of difference of the present embodiment from the above-mentioned ninth embodiment resides in the constitution whereby the number of the selection lines of the lower data encoder 255 is reduced to only one line, i.e., LN₂₁₄, to generate only one selection signal SEL₁₁₁ selected from among the selection signals, and a signal obtained by inverting the level of the selection signal SEL₁₁₁ at the inverter 259 is supplied as the signal in place of the selection signal SEL₁₀₂ to the other input of the AND gate A₁₁₂ of the selection gate 257 and output as the lower data conversion code D₂ of the upper significant bit data.

According to the present 10th embodiment, in addition to the effect of the above-described first embodiment, a simpler structure can be realized, and the chip area can be further reduced.

Note that, in the above-mentioned ninth and 10th embodiments, an explanation was made taking as an example an A/D converter circuit for four bits, but needless to say the present invention can be applied to an A/D converter circuit for more bits.

Also, in the above-mentioned ninth and 10th embodiments, the structure in which the other output pin buffers are arranged on the input side of the upper data encoder and the lower data encoder was indicated, but these other output pin buffers are provided so as to reliably drive the upper data encoder and the lower data encoder, and it is necessary to provide the same according to a certain capacitance of the upper data encoder and the lower data encoder acting as a so-called load.

As explained above, according to the present invention, there are advantages such that the inverted gate and inhibit gate which have been conventionally necessary become unnecessary, and the increase of speed of conversion processing can be achieved. In addition to the fact that the inverted gate and inhibit gate become unnecessary, the number of the selection signals can be reduced, and the number of the upper data codes to be selected and the number of the input gates of selection gates can be reduced, and therefore there is an advantage in that the reduction of the chip area and the reduction of the power consumption can be achieved.

FIGS. 30A-30C are circuit diagrams showing an 11th embodiment of the A/D converter circuit according to the present invention.

In FIG. 30, 270 denotes a matrix circuit; 271 to 274 denote upper data comparators; 275, an upper data encoder; 281 to 287 denote lower data comparators; 276, a lower data encoder; 279, a selection gate; 278, an inverter; R₂₄₁ to R₂₅₆ denote reference resistance elements; BU₁₃₁ to BU₁₃₅ and BD₁₄₁ and BD₁₄₇ denote multiple output pin buffers; OR₁₂₁ and OR₁₂₂ denote OR gates; and EXO₁₂₁ and EXO₁₂₂ denote exclusive-OR gates; respectively.

The matrix circuit 270 is constituted by the arrangement of 35 switching blocks S_(k11) to S_(k17), S_(k21) to S_(k27), S_(k31) to S_(k37), S_(k41) to S_(k47), and S_(k51) to S_(k57) in the form of a matrix comprising five rows and seven columns.

The respective switching blocks S_(k11) to S_(k17), S_(k21) to S_(k27), S_(k31) to S_(k37), S_(k41) to S_(k47), and S_(k51) to S_(k57) are constituted by differential type amplifiers comprising the npn-type transistors Q₂₃₁, Q₂₃₂, and Q₂₃₃.

Excluding the switching blocks S_(k11) to S_(k14) and S_(k54) to S_(k57), a reference voltage obtained by dividing the reference voltages V_(RT) to V_(RB) by the reference resistance elements R₂₄₁ to R₂₅₆ are supplied to the base of one side transistors Q₂₃₁ constituting a so-called differential pair of the respective switching blocks, and analog signals V_(IN) which should be converted to the digital code are supplied to the base of the other side transistors Q₂₃₂, respectively.

Also, the emitters of the transistors Q₂₃₁ and Q₂₃₂ are connected to each other, and the middle point of connection thereof is connected to the current source I via the transistor Q₂₃₃ switched by the control signals x₁₃₁ to x₁₃₅, respectively.

Also, to the collectors of the transistors Q₂₃₁ and Q₂₃₂, the power source voltage V_(DD) is supplied via the resistance element r, the output of which is respectively input to the comparators CD₁₄₁ to CD₁₄₇ of the seven lower data comparators 281 to 287 as mentioned later, which act also as the initial stage amplifiers of the lower data comparators 281 to 287.

Also, the collectors of the transistors Q₂₃₁ and Q₂₃₂ of the switching blocks at the second row and the fourth row from the bottom of the diagram are connected to the line in an opposite direction to that for the collector output of the transistors Q₂₃₁ and Q₂₃₂ of the switching blocks of the first row and third row, and steps are taken so that the line of the serial reference resistance elements R₂₄₁ to R₂₅₆ to which the reference potentials V_(RT) to V_(RB) are applied can be formed by folding-back.

The reference resistance elements R₂₄₁ to R₂₅₆ are serially connected between the two reference potentials V_(RT) and V_(RB) and arranged by folding-back so as to extend over a predetermined number of rows, e.g., five rows in the present embodiment to correspond to the matrix arrangement of the switching blocks in the matrix circuit 270.

Concretely, each two resistance elements R₂₅₆ and R₂₅₅ and R₂₄₂ and R₂₄₁ are serially connected at the first row and the fifth row from the bottom in the diagram, and the resistance elements R₂₅₄ to R₂₅₁, R₂₅₀ to R₂₄₇, and R₂₄₆ to R₂₄₃ are serially connected at the second row to the fourth row, respectively.

Viewing this folding-back arrangement of the resistance element columns from the reference potential V_(RB) terminal side positioned on the left end and lower end side of the matrix circuit 270, the wiring pattern extended in the right direction in the diagram is folded-back between the switching block column of the fourth column from the left in the diagram and the switching block column of the fifth column, and two resistance elements R₂₅₆ and R₂₅₅ are connected in series corresponding to the arrangement position of the switching blocks S_(k54) and S_(k53) at the first row from the bottom, whereby the first row of resistance column is constituted.

The resistance column at the first row is folded-back between the switching block column of the third column and the switching block column of the second column, and four resistance elements R₂₅₄ to R₂₅₁ are connected in series between the switching block rows of the first row and the second row and corresponding to the arrangement position of the switching blocks S_(k43) to S_(k46) of the second row, whereby the resistance column of the second row is constituted.

The resistance column of the second row is folded-back between the switching block column of the fifth column and the switching block column of the sixth column, and four resistance elements R₂₅₀ to R₂₄₇ are connected in series between the switching block rows of the second row and the third row and corresponding to the arrangement position of the switching blocks S_(k36) to S_(k33) of the third row, whereby the resistance column of the third row is constituted.

The resistance column of the third row is folded-back between the switching block column of the third column and the switching block column of the second column, and four resistance elements R₂₄₆ to R₂₄₃ are connected in series between the switching block rows of the fourth row and the fifth row and corresponding to the arrangement position of the switching blocks S_(k23) to S_(k26) of the fourth row, whereby the resistance column of the fourth row is constituted.

The resistance column of the fourth row is folded-back between the switching block column of the fifth column and the switching block column of the sixth column, two resistance elements R₂₄₂ and R₂₄₁ are connected in series between the switching block rows of the fourth row and the fifth row and corresponding to the arrangement position of the switching blocks S_(k16) to S_(k15) at the fifth row, and one end of the resistance element R₁ is connected to the terminal of the reference potential V_(RT), whereby the resistance column of the fifth row is constituted.

Namely, the resistance columns of the first row and the fifth row are arranged with a deviation of a half cycle with respect to the resistance columns of the second row to the fourth row so that the position exhibiting the lowest value of the reference voltage (connection point between the reference potential V_(RB) terminal and the resistance element R₂₅₆) and the position exhibiting the highest value (connection point between the reference potential V_(RT) terminal and the resistance element R₂₄₁) are positioned at an intermediate point in the row direction of the switching blocks arranged in the form of the matrix.

In such an arrangement structure of resistance columns, the switching block columns comprising seven columns are divided into two groups, i.e., the group comprising the switching block columns of from the first column to the fourth column and the group of the switching block columns of from the fifth column to the seventh column at the switching point between the upper data and lower data as will be mentioned later.

Also, the voltages V₂₈₁ to V₂₈₄ generated between the rows of the respective resistance columns are supplied to the upper data comparators 271 to 274 as the reference voltages obtained by dividing the reference potentials V_(RT) to V_(RB) by rough quantization, respectively.

In the structure of FIG. 30, when assuming that the voltage between the reference potentials V_(RT) to V_(RB) is V_(REF), the respective reference voltages V₂₈₁ to V₂₈₄ become the following values:

    V.sub.281 =(14/16)·V.sub.REF

    V.sub.282 =(10/16)·V.sub.REF

    V.sub.283 =(6/16)·V.sub.REF

    V.sub.284 =(2/16)·V.sub.REF

Further, wiring is carried out so that the respective reference voltages V₂₆₁ to V₂₇₅ divided by the reference resistance elements R₂₄₁ to R₂₅₆ are supplied to the base of the transistor Q₂₃₁ of the predetermined switching block.

Concretely, a reference voltage V₂₆₁ [=(15/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₄₁ and R₂₄₂ is supplied to the bases of the transistors Q₂₃₁ of the switching blocks S_(k15) and S_(k27).

A reference voltage V₂₆₂ [=V₂₈₁ =(14/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₄₂ and R₂₄₃ is supplied to the bases of the transistors Q₂₃₁ of the switching blocks S_(k16) and S_(k26).

A reference voltage V₂₆₃ [=(13/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₄₃ and R₂₄₄ is supplied to the bases of the transistors Q₂₃₁ of the switching blocks S_(k17) and S_(k25).

A reference voltage V₂₆₄ [=(12/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₄₄ and R₂₄₅ is supplied to the base of the transistor Q₂₃₁ of the switching block S_(k24).

A reference voltage V₂₆₅ [=(11/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₄₅ and R₂₄₆ is supplied to the bases of the transistors Q₂₃₁ of the switching blocks S_(k23) and S_(k31).

A reference voltage V₂₆₆ [=V₂₈₂ =(10/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₄₆ and R₂₄₇ is supplied to the bases of the transistors Q₂₃₁ of the switching blocks S_(k22) and S_(k32).

A reference voltage V₂₆₇ [=(9/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₄₇ and R₂₄₈ is supplied to the bases of the transistors Q₂₃₁ of the switching blocks S_(k21) and S_(k33).

A reference voltage V₂₆₈ [=(8/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₄₈ and R₂₄₉ is supplied to the base of the transistor Q₂₃₁ of the switching block S_(k34).

A reference voltage V₂₆₉ [=(7/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₄₉ and R₂₅₀ is supplied to the bases of the transistors Q₂₃₁ of the switching blocks S_(k35) and S_(k47).

A reference voltage V₂₇₀ [=V₂₈₃ =(6/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₅₀ and R₂₅₁ is supplied to the bases of the transistors Q₂₃₁ of the switching blocks S_(k36) and S_(k46).

A reference voltage V₂₇₁ [=(5/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₅₁ and R₂₅₂ is supplied to the bases of the transistors Q₂₃₁ of the switching blocks S_(k37) and S_(k45).

A reference voltage V₂₇₂ [=(4/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₅₂ and R₂₅₃ is supplied to the base of the transistor Q₂₃₁ of the switching block S_(k44).

A reference voltage V₂₇₃ [=(3/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₅₃ and R₂₅₄ is supplied to the bases of the transistors Q₂₃₁ of the switching blocks S_(k43) and S_(k51).

A reference voltage V₂₇₄ [=V₂₈₄ =(2/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₅₄ and R₂₅₅ is supplied to the bases of the transistors Q₂₃₁ of the switching blocks S_(k42) and S_(k52).

A reference voltage V₂₇₅ [=(1/16)·V_(REF) ] generated at the connection point between the resistance elements R₂₅₅ and R₂₅₆ is supplied to the bases of the transistors Q₂₃₁ of the switching blocks S_(k41) and S_(k53).

Upper data comparators 271, 272, 273, and 274 respectively are provided with comparators CU₁₃₁ to CU₁₃₄, complementary-type output amplifiers CA₁₃₁ to CA₁₃₄, and AND gates AU₁₃₁ to AU₁₃₄.

An analog signal V_(IN) is supplied to one input of the comparator CU₁₃₁ of the upper data comparator 271, and a reference voltage V₂₈₁ [=(14/16)·V_(REF) ] obtained by dividing the reference potentials V_(RT) to V_(RB) by rough quantization is supplied to the other input.

The analog signal V_(IN) is supplied to one input of the comparator CU₁₃₂ of the upper data comparator 272, and a reference voltage V₂₈₂ [=(10/16)·V_(REF) ] obtained by dividing the reference potentials V_(RT) to V_(RB) by rough quantization is supplied to the other input.

The analog signal V_(IN) is supplied to one input of the comparator CU₁₃₃ of the upper data comparator 273, and a reference voltage V₂₈₃ [=(6/16)·V_(REF) ] obtained by dividing the reference potentials V_(RT) to V_(RB) by rough quantization is supplied to the other input.

The analog signal V_(IN) is supplied to one input of the comparator CU₁₃₄ of the upper data comparator 274, and a reference voltage V₂₈₄ [=(2/16)·V_(REF) ] obtained by dividing the reference potentials V_(RT) to V_(RB) by rough quantization is supplied to the other input.

The output of the comparator CU₁₃₁ of the upper data comparator 271 is connected to the input of the output amplifier CA₁₃₁, the positive output thereof is connected to both inputs of a 2-input AND gate AU₁₃₁, and the negative output is connected to one input of the 2-input AND gate AU₁₃₂ of the upper data comparator 272.

The output of the comparator CU₁₃₂ of the upper data comparator 272 is connected to the input of the output amplifier CA₁₃₂, the positive output thereof is connected to the other input of the 2-input AND gate AU₁₃₂, and the negative output is connected to one input of the 2-input AND gate AU₁₃₃ of the upper data comparator 273.

The output of the comparator CU₁₃₃ of the upper data comparator 273 is connected to the input of the output amplifier CA₁₃₃, the positive output thereof is connected to the other input of a 2-input AND gate AU₁₃₃, and the negative output is connected to one input of the 2-input AND gate AU₁₃₄ of the upper data comparator 274.

The output of the comparator CU₁₃₄ of the upper data comparator 274 is connected to the input of the output amplifier CA₁₃₄, the positive output thereof is connected to the other input of a 2-input AND gate AU₁₃₄, and the negative output is connected to the both inputs of the 2-input AND gate AU₁₃₅.

The outputs of the respective comparators CU₁₃₁ to CU₁₃₄ of the upper data comparators 271 to 274 constituted in this way become the level of "H" or "L" corresponding to the level of the sampled analog signal V_(IN), and only one among the respective AND gates AU₁₃₁ to AU₁₃₄ outputs the "1" level.

The output of the AND gate AU₁₃₁ of the upper data comparator 271 is connected via the buffer BU₁₃₁ to the upper data encoder 275 and, at the same time, connected to the bases of the transistors Q₂₃₃ of the switching blocks S_(k11) to S_(k17) and connected to the input of the inverter 278 via the buffer.

The AND gate AU₁₃₂ of the upper data comparator 272 is connected via the buffer BU₁₃₂ to the upper data encoder 275 and, at the same time, connected to the bases of the transistors Q₂₃₃ of the switching blocks S_(k21) to S_(k27).

The output of the AND gate AU₁₃₃ of the upper data comparator 273 is connected via the buffer BU₁₃₃ to the upper data encoder 275 and, at the same time, connected to the bases of the transistors Q₂₃₃ of the switching blocks S_(k31) to S_(k37) and connected to the input of the inverter 278 via the buffer.

The AND gate AU₁₃₄ of the upper data comparator 274 is connected via the buffer BU₁₃₄ to the upper data encoder 275 and, at the same time, connected to the bases of the transistors Q₂₃₃ of the switching blocks S_(k41) to S_(k47).

The output of the AND gate AU₁₃₅ is connected to the input of the buffer BU₁₃₅ and, at the same time, connected to the bases of the transistors Q₂₃₃ of the switching blocks S_(k51) to S_(k57) and connected to the input of the inverter 278 via the buffer.

The upper data encoder 275 is constituted by an encoder line LN₂₂₁ generating the data for an L (left) mode and an encoder line LN₂₂₂ generating the data for an R (right) mode.

Namely, in the upper data encoder 275, respective encoder lines LN₂₂₁ and LN₂₂₂ are set corresponding to a first group of from the first column to the fourth column arranged on the left side from the center of the matrix circuit 270 and a second group of from the fifth column to the seventh column arranged on the right side among the switching blocks S_(k11) to S_(k17), S_(k21) to S_(k27), S_(k31) to S_(k37), S_(k41) to S_(k47) and S_(k51) to S_(k57) arranged in the matrix circuit 270.

FIG. 31 shows the correspondence between the outputs of the respective AND gates AU₁₃₁, AU₁₃₂, AU₁₃₃, AU₁₃₄, and AU₁₃₅ of the upper data comparators 271 to 274 and the set output data code pattern of the respective encoder lines LN₂₂₁ and LN₂₂₂ of the upper data encoder 275.

The setting of the data is carried out in such a manner that, in accordance with the direction of transition of the reference voltage level by the respective reference resistance elements in the rows among the serially connected reference resistance element groups which are folding-arranged so that the number of rows becomes five, concretely an orientation (hereinafter referred to as a direction) of transition of the reference voltage from the low potential side to the high potential side, so that (data of L mode)≧(data of R mode) and (data of L mode)≦(data of R mode) stands.

In the structure of FIG. 30, the first row from the bottom comprising the resistance elements R₂₅₆ and R₂₅₅, the third row comprising the resistance elements R₂₅₀ to R₂₄₇, and the fifth row comprising the resistance elements R₂₄₂ and R₂₄₁ have the same direction, and the second row comprising the resistance elements R₂₅₄ to R₂₅₁ and the fourth row comprising the resistance elements R₂₄₆ to R₂₄₃ have the same direction.

Accordingly, the data setting level in the case where the AND gates AU₁₃₅, AU₁₃₃, and AU₁₃₁ corresponding to the first row, third row, and fifth row are at the "1" level is set so that the data of the L mode becomes equal to or larger than the data of the R mode.

Contrary to this, the data setting level in the case where the AND gates AU₁₃₄ and AU₁₃₂ corresponding to the second row and the fourth row are at the "1" level is set so that the data of the L mode becomes equal to or smaller than the data of the R mode.

The lower data comparators 281 to 287 respectively are provided with comparators CD₁₄₁ to CD₁₄₇, complementary-type output amplifiers CA₁₄₁ to CA₁₄₇ , and AND gates AD₁₄₁ to AD₁₄₇.

To one input of the comparator CD₁₄₁ of the lower data comparator 281 is supplied the collector output of the transistors Q₂₃₁ of the switching blocks S_(k11), S_(k31), and S_(k51) at the first column of the matrix circuit 270 and the collector outputs of the transistors Q₂₃₂ of the switching blocks S_(k21) and S_(k41), and to the other input is supplied the collector outputs of the transistors Q₂₃₁ of the switching blocks S_(k21) and S_(k41) and the collector outputs of the transistors Q₂₃₂ of the switching blocks S_(k11), S_(k31), and S_(k51).

To one input of the comparator CD₁₄₂ of the lower data comparator 282 is supplied the collector output of the transistors Q₂₃₁ of the switching blocks S_(k12), S_(k32), and S_(k52) of the second column of the matrix circuit 270 and the collector outputs of the transistors Q₂₃₂ of the switching blocks S_(k22) and S_(k42), and to the other input is supplied the collector outputs of the transistors Q₂₃₁ of the switching blocks S_(k22) and S_(k42) and the collector outputs of the transistors Q₂₃₂ of the switching blocks S_(k12), S_(k32), and S_(k52).

To one input of the comparator CD₁₄₃ of the lower data comparator 283 is supplied the collector output of the transistors Q₂₃₁ of the switching blocks S_(k13), S_(k33), and S_(k53) at the third column of the matrix circuit 270 and the collector outputs of the transistors Q₂₃₂ of the switching blocks S_(k23) and S_(k43), and to the other input is supplied the collector outputs of the transistors Q₂₃₁ of the switching blocks S_(k23) and S_(k43) and the collector outputs of the transistors Q₂₃₂ of the switching blocks S_(k13), S_(k33), and S_(k53).

To one input of the comparator CD₁₄₄ of the lower data comparator 284 is supplied the collector output of the transistors Q₂₃₁ of the switching blocks S_(k14), S_(k34), and S_(k54) of the fourth column of the matrix circuit 270 and the collector outputs of the transistors Q₂₃₂ of the switching blocks S_(k24) and S_(k44), and to the other input is supplied the collector outputs of the transistors Q₂₃₁ of the switching blocks S_(k24) and S_(k44) and the collector outputs of the transistors Q₂₃₂ of the switching blocks S_(k14), S_(k34), and S_(k54).

To one input of the comparator CD₁₄₅ of the lower data comparator 285 is supplied the collector output of the transistors Q₂₃₁ of the switching blocks S_(k15), S_(k35), and S_(k55) at the fifth column of the matrix circuit 270 and the collector outputs of the transistors Q₂₃₂ of the switching blocks S_(k25) and S_(k45), and to the other input is supplied the collector outputs of the transistors Q₂₃₁ of the switching blocks S_(k25) and S_(k45) and the collector outputs of the transistors Q₂₃₂ of the switching blocks S_(k15), S_(k35), and S_(k55).

To one input of the comparator CD₁₄₆ of the lower data comparator 286 is supplied the collector output of the transistors Q₂₃₁ of the switching blocks S_(k16), S_(k36), and S_(k56) at the sixth column of the matrix circuit 270 and the collector outputs of the transistors Q₂₃₂ of the switching blocks S_(k26) and S_(k46), and to the other input is supplied the collector outputs of the transistors Q₂₃₁ of the switching blocks S_(k26) and S_(k46) and the collector outputs of the transistors Q₂₃₂ of the switching blocks S_(k16), S_(k36), and S_(k56).

To one input of the comparator CD₁₄₇ of the lower data comparator 287 is supplied the collector output of the transistors Q₂₃₁ of the switching blocks S_(k17), S_(k37), and S_(k57) at the seventh column of the matrix circuit 270 and the collector outputs of the transistors Q₂₃₂ of the switching blocks S_(k27) and S_(k47), and to the other input is supplied the collector outputs of the transistors Q₂₃₁ of the switching blocks S_(k27) and S_(k47) and the collector outputs of the transistors Q₂₃₂ of the switching blocks S_(k17), S_(k37), and S_(k57).

The output of the comparator CD₁₄₁ of the lower data comparator 281 is connected to the input of the output amplifier CA₁₄₁, the positive output thereof is connected to both inputs of the 2-input AND gate AD₁₄₁, and the negative output is connected to one input of the 2-input AND gate AD₁₄₂ of the lower data comparator 282.

The output of the comparator CD₁₄₂ of the lower data comparator 282 is connected to the input of the output amplifier CA₁₄₂, the positive output thereof is connected to the other input of the 2-input AND gate AD₁₄₂, and the negative output is connected to one input of the 2-input AND gate AD₁₄₃ of the lower data comparator 283.

The output of the comparator CD₁₄₃ of the lower data comparator 283 is connected to the input of the output amplifier CA₁₄₃, the positive output thereof is connected to the other input of the 2-input AND gate AD₁₄₃, and the negative output is connected to one input of the 2-input AND gate AD₁₄₄ of the lower data comparator 284.

The output of the comparator CD₁₄₄ of the lower data comparator 284 is connected to the input of the output amplifier CA₁₄₄, the positive output thereof is connected to the other input of the 2-input AND gate AD₁₄₄, and the negative output is connected to one input of the 2-input AND gate AD₁₄₅ of the lower data comparator 285.

The output of the comparator CD₁₄₅ of the lower data comparator 285 is connected to the input of the output amplifier CA₁₄₅ , the positive output thereof is connected to the other input of the 2-input AND gate AD₁₄₅, and the negative output is connected to one input of the 2-input AND gate AD₁₄₆ of the lower data comparator 286.

The output of the comparator CD₁₄₆ of the lower data comparator 286 is connected to the input of the output amplifier CA₁₄₆, the positive output thereof is connected to the other input of the 2-input AND gate AD₁₄₆, and the negative output is connected to one input of the 2-input AND gate AD₁₄₇ of the lower data comparator 287.

The output of the comparator CD₁₄₇ of the lower data comparator 287 is connected to the input of the output amplifier CA₁₄₇, the positive output thereof is connected to the other input of the 2-input AND gate AD₁₄₇, and the negative output is connected to both inputs of the 2-input AND gate AD₁₄₈.

The outputs of the respective comparators CD₁₄₁ to CD₁₄₇ of the lower data comparators 281 to 287 constituted in this way become the level of "H" or "L" corresponding to the level of 2 inputs, and only one of the respective AND gates AD₁₄₁ to AD₁₄₈ outputs the "1" level.

The outputs of the AND gates AD₁₄₁ to AD₁₄₇ and AD₁₄₈ of the lower data comparators 281 to 287 are connected via the buffers BD₁₄₁ to BD₁₄₈ to the lower data encoder 276.

The lower data encoder 276 is constituted by a data line LN₂₂₃ generating lower significant data BD₁₅₃ and BD₁₅₄ ; a selection line LN₂₂₄ generating the selection signal SEL₁₂₁ indicating that one of the outputs of the AND gates AD₁₄₁ to AD₁₄₄ of the lower data comparators 281 to 284 becomes "1"; and a selection line LN₂₂₅ generating the selection signal SEL₁₂₂ indicating that one of the outputs of the AND gates AD₁₄₅ to AD₁₄₇ and AD₁₄₈ of the lower data comparators 285 to 287 becomes "1".

FIG. 32 shows the correspondence between the outputs of the AND gates AD₁₄₁ to AD₁₄₅ on the upper data side and the outputs of the AND gates AD₁₄₁ to AD₁₄₈ on the lower data side and the output conversion code data.

As mentioned above, in the matrix circuit 170 in the present embodiment, the respective switching blocks are divided into two in the row direction. At this division point C, as seen from FIG. 32, when paying attention to the upper significant 2 bits of the output conversion codes D₁ to D₄, the division is made at the point at which the value of the upper significant 2 bits is switched.

The selection gate 279 is constituted by AND gates A₁₂₁ to A₁₂₄, selects a single upper significant data from among the respective upper significant data of the L mode and R mode output from the upper data encoder 275 using the selection signals SEL₁₂₁ and SEL₁₂₂ output from the lower data encoder 276, and outputs the same via the OR-gates OR₁₂₁ and OR₁₂₂ as the conversion codes D₁ and D₂.

Concretely, one input terminal of the AND gate A₁₂₁ is connected to one line (upper data side) of the encoder line LN₂₂₁ generating the data for the L mode of the upper data encoder 275, and the other input terminal is connected to the selection line LN₂₂₄ outputting the selection signal SEL₁₂₁ of the lower data encoder 276.

One input terminal of the AND gate A₁₂₂ is connected to one line (upper data side) of the encoder line LN₂₂₂ generating the data for the R mode of the upper data encoder 275, and the other input terminal is connected to the selection line LN₂₂₃ outputting the selection signal SEL₁₂₂ of the lower data encoder 276.

The outputs of these AND gates A₁₂₁ and A₁₂₂ are connected to the respective input terminals of the 2-input OR-gate OR₁₂₁.

One input terminal of the AND gate A₁₂₃ is connected to the other line (lower data side) of the encoder line LN₂₂₁ generating the data for the L mode of the upper data encoder 275, and the other input terminal is connected to the selection line LN₂₂₄ outputting the selection signal SEL₁₂₁ of the lower data encoder 276.

One input terminal of the AND gate A₁₂₄ is connected the other line (lower data side) of the encoder line LN₂₂₂ generating the data for the R mode of the upper data encoder 275, and the other input terminal is connected to the selection line LN₂₂₅ outputting the selection signal SEL₁₂₂ of the lower data encoder 276.

The outputs of these AND gates A₁₂₃ and A₁₂₄ are connected to the respective input terminals of the 2-input OR-gate OR₁₂₂.

The exclusive-OR gate EXO₁₂₁ obtains the exclusive-OR between the lower significant data BD₁₅₃ output from one line of the data line LN₂₂₃ of the lower data encoder 276 and the signal obtained by inverting the sum of output levels of the AND gates AU₁₃₁, AU₁₃₃, or AU₁₃₅ of the upper data comparators 271 and 273 by the inverter 278, and outputs the result thereof as the lower data conversion code D₃.

The exclusive-OR gate EXO₁₂₂ obtains the exclusive-OR between the lower significant data BD₁₅₄ output from the other line of the data line LN₂₂₃ of the lower data encoder 276 and the signal obtained by inverting the sum of output levels of the AND gates AU₁₃₁, AU₁₃₃, or AU₁₃₅ of the upper data comparators 271 and 273 by the inverter 278 and outputs the result thereof as the lower data conversion code D₄.

Next, an explanation will be made of the operation by the above-described structure.

For example, when the sampling voltage V_(S) of the sampled analog signal is represented as V_(RB) <V_(S) <V₂₈₄, the outputs of the comparators CU₁₃₁ to CU₁₃₄ of the upper data comparators 271 to 274 become all "L", so that the digital signals are output, i.e., "0" is output from the AND gates AU₁₃₁ to AU₁₃₄, and "1" is output from the AND gate AU₁₃₅, respectively.

As a result, a digital signal such as [0000] is input to the upper data encoder 275. At the upper data encoder 275, using a so-called wired-OR circuit, the upper significant data of [00] are generated in two columns of encoder lines [LN₂₂₁ ] generating the redundant L mode data and two columns of encoder lines [LN₂₂₂ ] generating the redundant R mode data, respectively, which are output to the selection gate 275.

Also, when the sampling voltage V_(S) is represented as V₂₈₄ <V_(S) <V₂₈₃, the outputs of the comparators CU₁₃₁ to CU₁₃₃ of the upper data comparators 271 to 273 become "L", and the output of the comparator CU₁₃₄ of the upper data comparator 274 becomes "H", so that the digital signals are output, i.e., "0" is output from the AND gates AU₁₃₁ to AU₁₃₃ and AU₁₃₅ of the upper data comparators 271 to 273, and "1" is output from the AND gate AU₁₃₄ of the upper data comparator 274, respectively.

As a result, a digital signal such as [0001] is input to the upper data encoder 275. At the upper data encoder 275, using a so-called wired-OR circuit, the upper significant data are generated, i.e., [00] is generated in two columns of encoder lines [LN₂₂₁ ] generating the redundant L mode data, and [01] is generated in two columns of encoder lines [LN₂₂₂ ] generating the redundant R mode data, respectively, which are output to the selection gate 275.

Also, when the sampling voltage V_(S) is represented as V₂₈₃ <V_(S) <V₂₈₂, similarly digital signals are output, i.e., "0" is output from the upper data side AND gates AU₁₃₁, AU₁₃₂, AU₁₃₄, and AU₁₃₅, and "1" is output from the AND gate AU₁₃₃, respectively.

As a result, a digital signal such as [0010] is input to the upper data encoder 275, and the upper significant data are output, i.e., [10] is output from the line [LN₂₂₁ ], and [01] is output from the line [LN₂₂₂ ] to the selection gate 275.

Further, when the sampling voltage V_(S) is represented as V₂₈₂ <V_(S) <V₂₈₁, the digital signals are output, i.e., "0" is output from the upper data side AND gates AU₁₃₁, AU₁₃₃, AU₁₃₄, and AU₁₃₅, and "1" is output from the AND gate AU₁₃₂, respectively.

As a result, a digital signal such as [0100] is input to the upper data encoder 275, and the upper significant data are output, i.e., [10] is output from the line [LN₂₂₁ ], and [11] is output from the line [LN₂₂₂ ] to the selection gate 275.

Similarly, when the sampling voltage V_(S) is represented as V₂₈₁ <V_(S) <V_(RT), the digital signals are output, i.e., "0" is output from the upper data side AND gates AU₁₃₂, AU₁₃₃, AU₁₃₄, and AU₁₃₅, and "1" is output from the AND gate AU₁₃₁, respectively.

As a result, a digital signal such as [1000] is input to the upper data encoder 275, and the upper significant data are output, i.e., [11] is output from the line [LN₂₂₁ ], and [11] is output from the line [LN₂₂₂ ] to the selection gate 275.

In parallel with this, the transistors Q₂₃₃ of the respective switching blocks of the matrix circuit 270 connected to the control lines (x₁₃₁, x₁₃₂, x₁₃₃, x₁₃₄, and X₁₃₅) at which the digital output signal has become "1" among the respective AND gates AU.sub.(131, 132, 133, 134, 135) are controlled to turn ON in units of rows, and further a fine digitization of the quantization level is executed.

For example, when only the output of the AND gate AU₁₃₃ becomes the "1" level, the transistors Q₂₃₃ of the switching blocks S_(k31) to S_(k37) become ON, so that the reference voltages V₂₆₇ to V₂₇₀ (=V₂₈₃) divided by the reference resistors R₂₄₇ to R₂₅₁ and the sampling voltage V_(S) are differentially amplified at the switching blocks S_(k33) to S_(k36) and compared by the lower data comparators 281 to 287.

Similarly, when the output of the AND gate AU₁₃₂ is at the "1" level, the switching blocks S_(k21) to S_(k27) are activated, so that a differential amplification operation is performed, and the comparison by the lower data comparators 281 to 287 is carried out.

In this way, in the lower data conversion codes, the sampled voltage V_(S) and the reference voltage divided by the reference resistance of that row are compared in units of rows of the switching blocks, so that the digital signal in accordance with the result of comparison will be output from the AND gates AD₁₄₁ to AD₁₄₇ and AD₁₄₈ of the lower data comparators 281 to 287.

At this time, in a case where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₈₄ >V_(IN), and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as V_(RB) <V_(IN) <[(V₂₈₄ +V₂₈₃)/2], or in a case where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as V_(RB) <V_(IN) <[(V₂₈₄ +V₂₈₃)/2], or in a case where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₈₃ <V_(IN) <V₂₈₂, and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as [(V₂₈₃ +V.sub. 282)/2]<V_(IN) <[(V₂₈₁ +V₂₈₂)/2], or in a case where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₈₂ <V_(IN) <V₂₈₁, and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as [(V₂₈₃ +V₂₈₂)/2]<V_(IN) <[(V₂₈₁ +V₂₈₂)/2], in the lower data encoder 276, only the selection line LN₂₂₄ becomes "1".

As a result, the selection signal SEL₁₂₁ is input to the selection gate 279 as the "1" level, and the selection signal SEL₁₂₂ is input to the selection gate 279 as the "0" level.

In the selection gate 279, along with the fact that only the selection signal SEL₁₂₁ is input as the "1" level, only the AND gates A₁₂₁ and A₁₂₃ are activated.

To these AND gates A₁₂₁ and A₁₂₃, the bit data of the upper data side and lower data side of the upper significant data for the L mode generated in the line LN₂₂₁ of the upper data encoder 275 are respectively supplied.

Accordingly, in the selection gate 279, the respective bits of the upper significant data at the L mode are selected, and as a result, they are output as the upper significant data conversion codes D₁ and D₂ via the OR gates OR₁₂₁ and OR₁₂₂.

Concretely, when the sampling voltage V_(S) of the analog signal V_(IN) is defined as V_(RB) <V_(S) <V₂₈₄, the upper data conversion codes [D₁, D₂ ] are output as [00]; when V₂₈₄ <V_(S) <V₂₈₃ stands, the upper significant data conversion codes [D₁, D₂ ] are output as [00]; when V₂₈₃ <V_(S) <V₂₈₂ stands, the upper significant data conversion codes [D₁, D₂ ] are output as [10]; when V₂₈₂ <V_(S) <V₂₈₁ stands, the upper significant data conversion codes [D₁, D₂ ] are output as [10]; and when V₂₈₁ <V_(S) <V_(RT) stands, the upper significant data conversion codes [D₁, D₂ ] are output as [11].

Also, in the lower data encoder 276, when the output of the AND gate AD₁₄₁ of the lower data comparator 281 is "1", the lower significant data BD₁₅₃ and BD₁₅₄ are generated as [11]; when the output of the AND gate AD₁₄₂ of the lower data comparator 282 is "1", the lower significant data BD₁₅₃ and BD₁₅₄ are generated as [10]; when the output of the AND gate AD₁₄₃ of the lower data comparator 283 is "1", the lower significant data BD₁₅₃ and BD₁₅₄ are generated as [01]; and when the output of the AND gate AD₁₄₄ of the lower data comparator 284 is "1", the lower significant data BD₁₅₃ and BD₁₅₄ are generated as [00], the data BD₁₅₃ is output to the exclusive-OR gate EXO₁₂₁, and the data BD₁₅₄ is output to the exclusive-OR gate EXO₁₂₂.

In the exclusive-OR gates EXO₁₂₁ and EXO₁₂₂, when V₂₈₄ <V_(S) <V₂₈₃ and V₂₈₂ <V_(S) <V₂₈₁ stand, that is where the switching blocks S_(k41) to S_(k47) and S_(k21) to S_(k27) of the second row and fourth row from the bottom of the matrix circuit 270 are selected, since the direction of application of the reference voltage is the forward direction, the levels of the lower significant data are output as the lower significant data conversion codes D₃ and D₄ while inverting the output level of the lower data encoder 276.

Contrary to this, when V_(RB) <V_(S) <V₂₈₄, V₂₈₃ <V_(S) <V₂₈₂ and V₂₈₁ <V_(S) <V_(RT) stand, that is where the switching blocks S_(k51) to S_(k57), S_(k31) to S_(k37), and S_(k11) to S_(k17) at the first row, third row, and fifth row from the bottom of the matrix circuit 270 are selected, since the direction of application of the reference voltage is the inverse direction, the levels of the lower significant data are held at the output level of the lower data encoder 276 as they are and output as the lower significant data conversion codes D₃ and D₄.

Also, in a case where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₈₄ <V_(IN) <V₂₈₃, and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as [(V₂₈₄ V₂₈₃)/2]<V_(IN) <[(V₂₈₃ +V₂₈₂)/2], or in a case where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₈₃ <V_(IN) <V₂₈₂, and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as [(V₂₈₄ +V₂₈₃)/2]<V_(IN) <[(V₂₈₃ +V₂₈₂)/2], or in a case where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₈₂ <V.sub. IN <V₂₈₁, and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as [(V₂₈₂ +V₂₈₁)/2]<V_(IN) <V_(RT), or in a case where the input analog signal when converting the upper significant 2 bits D₁ and D₂ is defined as V₂₈₁ <V_(IN), and the input analog signal when converting the lower significant 2 bits D₃ and D₄ is defined as [(V₂ +V₂₈₁)/2]<V_(IN) <V_(RT), in the lower data encoder 276, only the selection line LN₂₂₅ becomes "1".

As a result, the selection signal SEL₁₂₂ is input to the selection gate 279 as the "1" level, and the selection signal SEL₁₂₁ is input to the selection gate 279 as the "0" level.

In the selection gate 279, along with the fact that only the selection signal SEL₁₂₂ is input as the "1" level, only the AND gates A₁₂₂ and A₁₂₄ are activated.

To these AND gates A₁₂₂ and A₁₂₄, the bit data of the upper data side and lower data side of the upper significant data for the R mode generated in the line LN₂₂₂ of the upper data encoder 275 are respectively supplied.

Accordingly, in the selection gate 279, the respective bits of the upper significant data at the R mode are selected, and as a result, they are output as the upper significant data conversion codes D₁ and D₂ via the OR gates OR₁₂₁ and OR₁₂₂.

Concretely, when the sampling voltage V_(S) of the analog signal V_(IN) is defined as V_(RB) <V_(S) <V₂₈₄, the upper data conversion codes [D₁, D₂ ] are output as [00]; when V₂₈₄ <V_(S) <V₂₈₃ stands, the upper significant data conversion codes [D₁, D₂ ] are output as [01]; when V₂₈₃ <V_(S) <V₂₈₂ stands, the upper significant data conversion codes [D₁, D₂ ] are output as [01]; when V₂₈₂ <V_(S) <V₂₈₁ stands, the upper significant data conversion codes [D₁, D₂ ] are output as [11]; and when V₂₈₁ <V_(S) <V_(RT) stands, the upper significant data conversion codes [D₁, D₂ ] are output as [11].

Also, in the lower data encoder 276, when the output of the AND gate AD₁₄₅ of the lower data comparator 285 is "1", the lower significant data BD₁₅₃ and BD₁₅₄ are generated as [11]; when the output of the AND gate AD₁₄₆ of the lower data comparator 286 is "1", the lower significant data BD₁₅₃ and BD₁₅₄ are generated as [10]; when the output of the AND gate AD₁₄₇ of the lower data comparator 287 is "1", the lower significant data BD₁₅₃ and BD₁₅₄ are generated as [01]; and when the output of the AND gate AD₁₄₈ is "1". the lower significant data BD₁₅₃ and BD₁₅₄ are generated as [00], the data BD₁₅₃ is output to the exclusive-OR gate EXO₁₂₁, and the data BD₁₅₄ is output to the exclusive-OR gate EXO₁₂₂.

In the exclusive-OR gates EXO₁₂₁ and EXO₁₂₂, when V₂₈₄ <V_(S) <V₂₈₃ and V₂₈₂ <V_(S) <V₂₈₁ stand, that is where the switching blocks S_(k41) to S_(k47) and S_(k21) to S_(k27) at the second row and fourth row from the bottom of the matrix circuit 270 are selected, since the direction of application of the reference voltage is the forward direction, the levels of the lower significant data are output as the lower significant data conversion codes D₃ and D₄ while inverting the output level of the lower data encoder 276.

Contrary to this, when V_(RB) <V_(S) <V₂₈₄, V₂₈₃ <V_(S) <V₂₈₂ and V₂₈₁ <V_(S) <V_(RT) stand, that is where the switching blocks S_(k51) to S_(k57), S_(k31) to S_(k37), and S_(k11) to S_(k17) at the first row, third row, and fifth row from the bottom of the matrix circuit 270 are selected, since the direction of application of the reference voltage is the inverse direction, the levels of the lower significant data are held at the output level of the lower data encoder 276 as they are and output as the lower significant data conversion codes D₃ and D₄.

As explained above, according to the present embodiment, the lower significant codes are divided into two groups, and the signals SEL₂₂₁ and SEL₂₂₂ for selecting the L mode data and R mode data are output from the lower data encoder 276 obtaining these groups of conversion code, so that the L mode data and R mode data output from the upper data encoder 275 are selected, thereby obtaining the upper data conversion codes D₁ and D₂, and therefore it is possible to use the selection signal directly for the selection of the upper significant data without the use of the inverted gate and inhibit gate as in the conventional circuit.

Accordingly, the input of the selection signal to the selection gate 275 is not delayed relative to the output of the upper data encoder 270, and thus the increase of speed of conversion processing can be achieved.

Also, in addition to the fact that the inverted gate and inhibit gate become unnecessary, the number of selection signals can be reduced to two, and also the number of the upper significant codes to be selected and the number of the input gates of the selection gates can be reduced to two, and therefore an A/D converter circuit with which the reduction of the surface area of the chip and the reduction of the power consumption can be achieved can be realized.

FIGS. 33A-33C are circuit diagrams showing a 12th embodiment of the A/D converter circuit according to the present invention.

The point of difference of the present embodiment from the above-mentioned 11th embodiment resides in the constitution whereby the number of the selection lines of the lower data encoder 306 is reduced to only one line, i.e., LN₂₅₂, to generate only one selection signal SEL₁₆₁ selected from among the selection signals, and a signal obtained by inverting the level of the selection signal SEL₁₆₁ at the inverter 309 is supplied as the signal in place of the selection signal SEL₁₂₂ to the other inputs of the AND gates A₁₅₂ and A₁₅₄ of the selection gate 307.

According to the present 12th embodiment, in addition to the effect of the above-described 11th embodiment, a simpler structure can be realized, and the chip area can be further reduced.

Note that, in the above-mentioned 11th and 12th embodiments, an explanation was made taking as an example an A/D converter circuit for four bits, but needless to say the present invention can be applied to an A/D converter circuit for more bits as well.

Also, in the above-mentioned 11th and 12th embodiments, the structure in which the other output pin buffers are arranged on the input side of the upper data encoder and the lower data encoder was indicated, but these other output pin buffers are provided so as to reliably drive the upper data encoder and the lower data encoder, and it is necessary to provide the same according to a certain capacitance of the upper data encoder and the lower data encoder acting as a so-called load.

As explained above, according to the present invention, there are advantages such that the inverted gate and inhibit gate which have been conventionally necessary become unnecessary, the increase of speed of conversion processing can be achieved. Also, in addition to the fact that the inverted gate and inhibit gate become unnecessary, the number of the selection signals can be reduced and the number of the upper data codes to be selected and the number of the input gates of selection gates can be reduced, so there is an advantage that the reduction of the chip area and the reduction of the power consumption can be achieved.

FIG. 34 is a circuit diagram showing a 13th embodiment of the A/D converter circuit according to the present invention.

In FIG. 34, 330 denotes a matrix circuit; 331 and 332 denote upper data comparators; 333, an upper data encoder; 341 to 348 denote lower data comparators; 334, a lower data encoder; 335, a selection gate; 336, an inverter; R₃₀₁ to R₃₁₆ denote reference resistance elements; r, a resistance element for load; BU₃₃₁ to BU₃₃₃ and BD₁₈₁ to BD₁₈₈ denote multiple output pin buffers; OR_(U171) to OR_(U174) denote upper data side 2-input OR-gates; OR_(D1) to OR_(D2) denote lower data side 2-input OR-gates; and OR₃₀₁ and OR₃₀₂ denote 2-input OR-gates for outputting the conversion code; respectively.

The matrix circuit 330 is constituted in the form of a so-called zigzag-shaped matrix comprising 4 rows and 8 columns in which two switching blocks selected from among 16 switching blocks S_(m12), S_(m14), S_(m16), S_(m18), S_(m21), S_(m23), S_(m25), S_(m27), S_(m32), S_(m34), S_(m36), S_(m38), and S_(m41), S_(m43), S_(m45), S_(m47) are arranged in each column.

The specific arrangement is one where the switching blocks S_(m12), S_(m14), S_(m16), and S_(m18) are arranged in the upper stage; the switching blocks S_(m21), S_(m23), S_(m25), and S_(m27) are arranged in the next stage; the switching blocks S_(m32), S_(m34), S_(m36), and S_(m38) are arranged in a lower stage than this; and the switching blocks S_(m41), S_(m43), S_(m45), and S_(m47) are arranged in the lowermost stage, and the switching blocks S_(m41), S_(m43), S_(m45) and S_(m47) and S_(m21), S_(m23), S_(m25) and S_(m27) arranged at the first row and third row from the bottom are formed into sets, whereby the first, third, fifth, and seventh columns are constituted; and the switching blocks S_(m32), S_(m34), S_(m36) and S_(m38) and S_(m12), S_(m14), S_(m16) and S_(m18) are formed into sets, whereby the second, fourth, sixth and eighth columns are constituted.

The respective switching blocks S_(m12), S_(m14), S_(m16), S_(m18), S_(m21), S_(m23), S_(m25), S_(m27), S_(m32), S_(m34), S_(m36), S_(m38), and S_(m41), S_(m43), S_(m45), S_(m47) are constituted by differential type amplifiers comprising the npn-type transistors Q₂₆₁, Q₂₆₂ and Q₂₆₃.

Reference voltages V₃₃₁ to V₃₄₅ obtained by dividing the reference voltages V_(RT) to V_(RB) by the reference resistance elements R₃₀₁ to R₃₁₆ are supplied to the base of one side transistors Q₂₆₁ constituting a so-called differential pair of the respective switching blocks, respectively, and analog signals V_(IN) which are to be converted to a digital code are supplied to the base of the other side transistors Q₂₆₂, respectively.

Also, the emitters of the transistors Q₂₆₁ and Q₂₆₂ are connected to each other, and the middle point of connection thereof is connected to the current source I via the transistor Q₂₆₃ switched by the control signals x₁₇₁ to x₁₇₄ of the OR-gates ORU₁₇₁ to ORU₁₇₄, respectively.

To the collectors of the transistors Q₂₆₁ and Q₂₆₂, the power source voltage V_(DD) is supplied via the resistance element r, the output of which is respectively input to the comparators CD₁₈₁ to CD₁₈₈ of the eight lower data comparators 341 to 348 as mentioned later, which act also as the initial stage amplifiers of the lower data comparators 341 to 348.

The reference resistance elements R₃₀₁ to R₃₁₆ are serially connected between the two reference potentials V_(RT) and V_(RB) and arranged by folding-back so as to extend over a predetermined number of rows, e.g., four rows in the present embodiment, to correspond to the matrix arrangement of the switching blocks in the matrix circuit 330.

Concretely, resistance elements R₃₁₆ to R₃₁₃ are serially connected at the first row from the bottom in the diagrams as to correspond to the switching blocks S_(m41), S_(m43), S_(m45) and S_(m47) ; resistance elements R₃₁₂ to R₃₀₉ are serially connected at the second row so as to correspond to the switching blocks S_(m32), S_(m34), S_(m36) and S_(m38) ; resistance elements R₃₀₈ to R₃₀₅ are serially connected at the third row so as to correspond to the switching blocks S_(m21), S_(m23), S_(m25) and S_(m27) ; and resistance elements R₃₀₄ to R₃₀₁ are serially connected at the fourth row so as to correspond to the switching blocks S_(m12), S_(m14), S_(m16) and S_(m18).

Also, the reference voltage V₃₃₁ (=V₃₅₁) generated at the middle point of connection between the resistance elements R₃₀₆ and R₃₀₇ constituting the resistance column at the third row from the bottom; and the reference voltage V₃₄₀ (=V₃₅₂) generated at the middle point of connection between the resistance elements R₃₁₀ and R₃₁₁ constituting the resistance column at the second row are supplied to the upper data comparators 331 and 332 as the reference voltages obtained by dividing the reference potentials V_(RT) to V_(RB) by rough quantization, respectively.

In the structure of FIG. 34, when assuming that the voltage between the reference potentials V_(RT) to V_(RB) is V_(REF), the respective reference voltages V₃₅₁ and V₃₅₂ become the following values, respectively:

    V.sub.336 =V.sub.351 =(10/16)·V.sub.REF

    V.sub.340 =V.sub.352 =(6/16)·V.sub.REF

Wiring is carried out so that the respective reference voltages V₃₃₁ to V₃₄₅ divided by the reference resistance elements R₃₀₁ to R₃₁₆ are supplied to the base of the transistor Q₂₆₁ of the predetermined switching block.

Concretely, a reference voltage V₃₃₁ [=(15/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₀₁ and R₃₀₂ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(M12).

A reference voltage V₃₃₂ [=(14/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₀₂ and R₃₀₃ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(m14).

A reference voltage V₃₃₃ [=(13/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₀₃ and R₃₀₄ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(m16).

A reference voltage V₃₃₄ [=(12/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₀₄ and R₃₀₅ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(m18).

A reference voltage V₃₃₅ [=(11/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₀₅ and R₃₀₆ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(m27).

A reference voltage V₃₃₆ [=V₃₅₁ =(10/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₀₆ and R₃₀₇ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(m25).

A reference voltage V₃₃₇ [=(9/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₀₇ and R₃₀₈ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(m23).

A reference voltage V₃₃₈ [=(8/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₀₈ and R₃₀₉ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(m21).

A reference voltage V₃₃₉ [=(7/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₀₉ and R₃₁₀ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(m32).

A reference voltage V₃₄₀ [=V₃₅₂ =(6/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₁₀ and R₃₁₁ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(m34).

A reference voltage V₃₄₁ [=(5/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₁₁ and R₃₁₂ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(m36).

A reference voltage V₃₄₂ [=(4/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₁₂ and R₃₁₃ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(m38).

A reference voltage V₃₄₃ [=(3/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₁₃ and R₃₁₄ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(m47).

A reference voltage V₃₄₄ [=(2/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₁₄ and R₃₁₅ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(m45).

A reference voltage V₃₄₅ [=(1/16)·V_(REF) ] generated at the connection point between the resistance elements R₃₁₅ and R₃₁₆ is supplied to the base of the transistor Q₂₆₁ of the switching block S_(m43).

Upper data comparators 331 and 332 respectively are provided with comparators CU₁₇₁ and CU₁₇₂, complementary-type output amplifiers CA₁₇₁ to CA₁₇₃ and AND gates AU₁₇₁ and AU₁₇₂.

An analog signal V_(IN) is supplied to one input of the comparator CU₁₇₁ of the upper data comparator 331, and a reference voltage V₃₅₁ [=V₃₃₆ =(10/16)·V_(REF) ] obtained by dividing the reference potentials V_(RT) to V_(RB) by rough quantization is supplied to the other input.

The analog signal V_(IN) is supplied to one input of the comparator CU₁₇₂ of the upper data comparator 332, and a reference voltage V₃₅₂ [=V₃₄₀ =(6/16)·V_(REF) ] obtained by dividing the reference potentials V_(RT) to V_(RB) by rough quantization is supplied to the other input.

The output of the comparator CU₁₇₁ of the upper data comparator 331 is connected to the input of the output amplifier CA₁₇₁, the positive output thereof is connected to both inputs of a 2-input AND gate AU₁₇₁, and the negative output is connected to one input of the 2-input AND gate AU₁₇₂ of the upper data comparator 332.

The output of the comparator CU₁₇₂ of the upper data comparator 332 is connected to the input of the output amplifier CA₁₇₂, the positive output thereof is connected to the other input of the 2-input AND gate AU₁₇₂, and the negative output is connected to one input of the 2-input AND gate AU₁₇₃.

The outputs of the respective comparators CU₁₇₁ and CU₁₇₂ of the upper data comparators 331 and 332 constituted in this way become the level of "H" or "L" corresponding to the level of the sampled analog signal V_(IN), and only one among the respective AND gates AU₁₇₁ to AU₁₇₃ outputs the "1" level.

The output of the AND gate AU₁₇₁ of the upper data comparator 331 is connected via the buffer BU₁₇₁ to the inputs of the upper data encoder 333 and inverter 336, and the 2-input OR-gate OR_(D1) on the lower significant side and, at the same time, connected to both inputs of the 2-input OR-gate OR_(U171) and one input of the 2-input OR-gate OR_(U172).

The output of the OR-gate OR_(U171) is supplied as the control signal x₁₇₁ to the bases of the transistors Q₂₆₃ of the switching blocks S_(m12), S_(m14), S_(m16), and S_(m18), and the output of the OR-gate OR_(U172) is supplied as the control signal x₁₇₂ to the bases of the transistors Q₂₆₃ of the switching blocks S_(m21), S_(m23), S_(m25) and S_(m27).

Accordingly, where the output of the AND gate AU₁₇₁ of the upper data comparator 331 becomes the "1" level (V₂₅₁ <V_(IN) <V_(RT)), the switching blocks S_(m21), S_(m23), S_(m25) and S_(m27) of the third row from the bottom and the switching blocks S_(m12), S_(m14), S_(m16) and S_(m18) of the fourth row are activated.

The output of the AND gate AU₁₇₂ of the upper data comparator 332 is connected via the buffer BU₁₇₂ to the inputs of the upper data encoder 333 and, at the same time, connected to the other input of the 2-input OR-gate OR_(U172) and one input of the 2-input OR-gate OR_(U173).

The output of the OR-gate OR_(U172) is supplied as the control signal x₁₇₂ to the bases of the transistors Q₂₆₃ of the switching blocks S_(m21), S_(m23), S_(m25) and S_(m27) as mentioned above, and the output of the OR-gate OR_(U173) is supplied as the control signal x₁₇₃ to the bases of the transistors Q₂₆₃ of the switching blocks S_(m32), S_(m34), S_(m36) and S_(m38).

Accordingly, where the output of the AND gate AU₁₇₂ of the upper data comparator 332 becomes the "1" level (V₃₅₂ <V_(IN) <V₃₅₁), the switching blocks S_(m21), S_(m23), S_(m25) and S_(m27) of the third row from the bottom and the switching blocks S_(m32), S_(m34), S_(m36) and S_(m38) of the second row are activated.

The output of the AND gate AU₁₇₃ is connected via the buffer BU₁₇₃ to the inputs of the upper data encoder 333 and inverter 336, and the 2-input OR-gate OR_(D1) on the lower data side and, at the same time, connected to the other input of the 2-input OR-gate OR_(U173) and both inputs of the 2-input OR-gate OR_(U174).

The output of the OR-gate OR_(U173) is supplied as the control signal x₁₇₃ to the bases of the transistors Q₂₆₃ of the switching blocks S_(m32), S_(m34), S_(m36) and S_(m38) as mentioned above, and the output of the OR-gate OR_(U174) is supplied as the control signal x₁₇₄ to the bases of the transistors Q₂₆₃ of the switching blocks S_(m41), S_(m42), S_(m43) and S_(m44).

Accordingly, where the output of the AND gate AU₁₇₃ becomes the "1" level (V_(RB) <V_(IN) <V₂₅₂), the switching blocks S_(m32), S_(m34), S_(m36) and S_(m38) at the second row from the bottom and the switching blocks S_(m41), S_(m43), S_(m45) and S_(m47) are activated.

The upper data encoder 333 is constituted by an encoder line LN₂₇₁ generating the data for the first mode, and an encoder line LN₂₇₂ generating the data for the second mode.

Namely, in the upper data encoder 333, respective encoder lines LN₂₇₁ and LN₂₇₂ are set in correspondence with a first group comprising switching block columns constituting odd number columns and a second group comprising switching block columns constituting even number columns among switching blocks S_(m12), S_(m14), S_(m16), S_(m18), S_(m21), S_(m23), S_(m25), S_(m27), S_(m32), S_(m34), S_(m36), S_(m38), and S_(m41), S_(m43), S_(m45), S_(m47) arranged in the matrix circuit 330.

FIG. 35 shows the correspondence between the outputs of the respective AND gates AU₁₇₁, AU₁₇₂ and AU₁₇₃ of the upper data comparators 331 and 332 and the set output data code pattern of the respective encoder lines LN₂₇₁ and LN₂₇₂ of the upper data encoder 333.

The setting of the data is basically determined by the data arrangement of FIG. 36 mentioned later, and the value of the set data is set so that, by using the generation position of the reference potential V_(RB), reference voltages V₃₃₂ and V₃₄₀ as the reference, in accordance with whether the direction of transition of the reference voltage level by the respective reference resistance elements, concretely an orientation (hereinafter referred to as a direction) of transition of the reference voltage from the low potential side to the high potential side is the right direction or left direction, so that the data of the first mode<the data of the second mode and the data of the first mode<the data of the second mode stand.

Accordingly, the data setting level in the case where the AND gates AU₁₇₃ and AU₁₇₁ are at the "1" level when V_(RB) <V_(IN) <V₃₄₀ (V₃₅₂) and V₃₃₆ (V₃₅₁)<V_(IN) <V_(RT) is set so that the data of the first mode<the data of the second mode stands.

Contrary to this, the data setting level in the case where the AND gate AU₁₇₂ is at the "1" level when V₃₄₀ (V₃₅₂)<V_(IN) <V₃₃₆ (V₃₅₁) is set so that the data of the first mode<the data of the second mode stands.

The lower data comparators 341 to 348 respectively are provided with comparators CD₁₈₁ to CD₁₈₈, complementary-type output amplifiers CA₁₈₁ to 188 and AND gates AD₁₈₁ to AD₁₈₈.

To one input of the comparator CD₁₈₁ of the lower data comparator 341 is supplied the collector outputs of the transistors Q₂₆₁ of the switching blocks S_(m21) and S_(m41) of the first column of the matrix circuit 330, while to the other input is supplied the collector outputs of the transistors Q₂₆₂ of the switching blocks S_(m21) and S_(m41).

To one input of the comparator CD₁₈₂ of the lower data comparator 342 is supplied the collector outputs of the transistors Q₂₆₁ of the switching blocks S_(m12) and S_(m32) of the second column of the matrix circuit 330, while to the other input is supplied the collector outputs of the transistors Q₂₆₂ of the switching blocks S_(m12) and S_(m32).

To one input of the comparator CD₁₈₃ of the lower data comparator 343 is supplied the collector outputs of the transistors Q₂₆₁ of the switching blocks S_(m23) and S_(m43) of the third column of the matrix circuit 330, while to the other input is supplied the collector outputs of the transistors Q₂₆₂ of the switching blocks S_(m23) and S_(m43).

To one input of the comparator CD₁₈₄ of the lower data comparator 344 is supplied the collector outputs of the transistors Q₂₆₁ of the switching blocks S_(m14) and S_(m34) of the fourth column of the matrix circuit 330, while to the other input is supplied the collector outputs of the transistors Q₂₆₂ of the switching blocks S_(m14) and S_(m34).

To one input of the comparator CD₁₈₅ of the lower data comparator 345 is supplied the collector outputs of the transistors Q₂₆₁ of the switching blocks S_(m25) and S_(m45) of the fifth column of the matrix circuit 330, while to the other input is supplied the collector outputs of the transistors Q₂₆₂ of the switching blocks S_(m25) and S_(m45).

To one input of the comparator CD₁₈₆ of the lower data comparator 346 is supplied the collector outputs of the transistors Q₂₆₁ of the switching blocks S_(m16) and S_(m36) at the sixth column of the matrix circuit 330, and to the other input is supplied the collector outputs of the transistors Q₂₆₂ of the switching blocks S_(m16) and S_(m36).

To one input of the comparator CD₁₈₇ of the lower data comparator 347 is supplied the collector outputs of the transistors Q₂₆₁ of the switching blocks S_(m27) and S_(m47) at the seventh column of the matrix circuit 330, and to the other input is supplied the collector outputs of the transistors Q₂₆₂ of the switching blocks S_(m27) and S_(m47).

To one input of the comparator CD₁₈₈ of the lower data comparator 348 is supplied the collector outputs of the transistors Q₂₆₁ of the switching blocks S_(m18) and S_(m38) at the eighth column of the matrix circuit 330, and to the other input is supplied the collector outputs of the transistors Q₂₆₂ of the switching blocks S_(m18) and S_(m38).

The output of the comparator CD₁₈₁ of the lower data comparator 341 is connected to the input of the output amplifier CA₁₈₁, the positive output thereof is connected to one input of the 2-input AND gate AD₁₈₁, and the negative output is connected to one input of the 2-input OR gate OR_(D1).

The outputs of the buffers BU₁₈₁ and BU₁₈₃ receiving the outputs of the AND gates AU₁₈₁ and AU₁₈₃ on the upper data side are connected to the other input of the OR-gate OR_(D1), and the output of the OR-gate OR_(D1) is connected to one input of the AND gate AD₁₈₂ of the lower data comparator 342.

The output of the comparator CD₁₈₂ of the lower data comparator 342 is connected to the input of the output amplifier CA₁₈₂, the positive output thereof is connected to the other input of the 2-input AND gate AD₁₈₂, and the negative output is connected to one input of the 2-input AND gate AD₁₈₄ of the lower data comparator 344.

The output of the comparator CD₁₈₃ of the lower data comparator 343 is connected to the input of the output amplifier CA₁₈₃, the positive output thereof is connected to one input of the 2-input AND gate AD₁₈₃, and the negative output is connected to the other input of the 2-input AND gate AD₁₈₁ of the lower data comparator 341.

The output of the comparator CD₁₈₄ of the lower data comparator 344 is connected to the input of the output amplifier CA₁₈₄, the positive output thereof is connected to the other input of the 2-input AND gate AD₁₈₄, and the negative output is connected to one input of the 2-input AND gate AD₁₈₆ of the lower data comparator 346.

The output of the comparator CD₁₈₅ of the lower data comparator 345 is connected to the input of the output amplifier CA₁₈₅, the positive output thereof is connected to one input of the 2-input AND gate AD₁₈₅, and the negative output is connected to the other input of the 2-input AND gate AD₁₈₃ of the lower data comparator 343.

The output of the comparator CD₁₈₆ of the lower data comparator 346 is connected to the input of the output amplifier CA₁₈₆, the positive output thereof is connected to one input of the 2-input AND gate AD₁₈₆, and the negative output is connected to one input of the 2-input AND gate AD₁₈₈ of the lower data comparator 348.

The output of the comparator CD₁₈₇ of the lower data comparator 347 is connected to the input of the output amplifier CA₁₈₇, the positive output thereof is connected to one input of the 2-input AND gate AD₁₈₇, and the negative output is connected to the other input of the 2-input AND gate AD₁₈₅ of the lower data comparator 345.

The output of the comparator CD₁₈₈ of the lower data comparator 348 is connected to the input of the output amplifier CA₁₈₈, the positive output thereof is connected to the other input of the 2-input AND gate AD₁₈₈, and the negative output is connected to one input of the 2-input OR gate OR_(D2).

The output of the inverter 336 inverting the output levels of the buffers BU₁₇₁ and BU₁₇₃ receiving the outputs of the AND gates AU₁₇₁ and AU₁₇₃ on the upper data side is connected to the other input of the OR-gate OR_(D2), and the output of the OR-gate OR_(D2) is connected to the other input of the AND gate AD₁₈₇ of the lower data comparator 347.

A so-called ring comparator is constituted by the lower data comparators 341 to 348 constituted in this way, the outputs of the respective comparators CD₁₈₁ to CD₁₈₈ become the level of "H" or "L" corresponding to the level of 2 inputs, and only one of the respective AND gates AD₁₈₁ to AD₁₈₈ outputs the active "1" level.

The outputs of the AND gates AD₁₈₁ to AD₁₈₈ of the lower data comparators 341 to 348 are connected via the buffers B_(D1) to B_(D8) to the lower data encoder 334.

The lower data encoder 334 is constituted by a data line LN₂₇₃ generating lower significant data D₃ and D₄ ; a selection line LN₂₇₄ generating the selection signal SEL₁₇₁ indicating that one of the outputs of the AND gates AD₁₈₁, AD₁₈₃, AD₁₈₅, and AD₁₈₇ of the lower data comparators 341, 343, 345 and 347 becomes "1"; and a selection line LN₂₇₅ generating the selection signal SEL₁₇₂ indicating that one of the outputs of the AND gates AD₁₈₂, AD₁₈₄, AD₁₈₆ and AD₁₈₈ of the lower data comparators 342, 344, 346 and 348 becomes "1"

FIG. 36 shows the correspondence between the outputs of the AND gates AU₁₈₁ to AU₁₈₃ on the upper data side and the outputs of the AND gates AD₁₈₁ to AD₁₈₈ on the lower data side and the output conversion code data.

As shown in FIG. 36, the upper data code is determined according to the row in the correspondence table.

Namely, in the table, it becomes [00], [01], [10] and [11] in sequence from the lowermost bit row.

Contrary to this, the lower bit codes are classified into two types, i.e., [0000] to [0011] and [0100] to [0111] in accordance with the row.

From above, the upper data code can be selected from two conditions that which among the upper data side AND gates AU₁₈₁ to AU₁₈₃ output "1" and which group of AND gate in the first group comprising the odd number of AND gates AD₁₈₁, AD₁₈₃, AD₁₈₅ and AD₁₈₇ and the second group comprising the even number of AND gates AD₁₈₂, AD₁₈₄, AD₁₈₆ and AD₁₈₈ among the respective AND gates AD₁₈₁ to AD₁₈₈ of the lower data comparators 341 to 348 output "1".

For example, where the upper data side AND gate AU₁₇₁ outputs "1", if there is one among the AND gates of the first group of the lower data comparator which outputs "1", [00] is selected as the upper data code, while if there is one among the AND gates of the second group which outputs "1", [01] is selected as the upper data code,

This selection of the upper data code is carried out at the selection gate 335.

The selection gate 335 is constituted by AND gates A₁₈₁ to A₁₈₄, selects one side upper significant data from among the respective upper significant data of the first mode and second mode output from the upper data encoder 333 using the selection signals SEL₁₇₁ and SEL₁₇₂ output from the lower data encoder 334, and outputs the same via the OR-gates OR₃₀₁ and OR₃₀₂ as the conversion codes D₁ and D₂.

Concretely, one input terminal of the AND gate A₁₈₁ is connected to one line (upper data side) of the encoder line LN₂₇₁ generating the data for the first mode of the upper data encoder 333, and the other input terminal is connected to the selection line LN₂₇₄ outputting the selection signal SEL₁₇₁ of the lower data encoder 334.

One input terminal of the AND gate A₁₈₂ is connected to one line (upper data side) of the encoder line LN₂₇₂ generating the data for the second mode of the upper data encoder 333, and the other input terminal is connected to the selection line LN₂₇₅ outputting the selection signal SEL₁₇₂ of the lower data encoder 334.

The outputs of these AND gates A₁₈₁ and A₁₈₂ connected to the respective input terminals of the 2-input OR-gate OR₃₀₁.

One input terminal of the AND gate A₁₈₃ is connected to the other line (lower data side) of the encoder line LN₂₇₁ generating the data for the first mode of the upper data encoder 333, and the other input terminal is connected to the selection line LN₁₇₂ outputting the selection signal SEL₁₇₁ of the lower data encoder 334.

One input terminal of the AND gate A₁₈₄ is connected to the other line (lower data side) of the encoder line LN₂₇₂ generating the data for the second mode of the upper data encoder 333, and the other input terminal is connected to the selection line LN₂₇₅ outputting the selection signal SEL₁₇₂ of the lower data encoder 334.

The outputs of these AND gates A₁₈₃ and A₁₈₄ are connected to the respective input terminals of the 2-input OR-gate OR₃₀₂.

Next, an explanation will be made of the operation by the above-described structure.

For example, when the sampling voltage V_(S) of the sampled analog signal is represented as V_(RB) <V_(S) <V₃₅₂ (=V₃₄₀), the outputs of the comparators CU₁₇₁ and CU₁₇₂ of the upper data comparators 331 and 332 become ("L"), so that the digital signals are output, i.e., "0" is output from the AND gates AU₁₇₁ and AU₁₇₂, and "1" is output from the AND gate AU₁₇₃, respectively.

As a result, a digital signal such as [001] is input to the upper data encoder 333 via the buffers BU₁₇₁ to BU₁₇₃. At the upper data encoder 133, using a so-called wired-OR circuit, the upper significant data [00] are generated in two columns of encoder lines [LN₂₇₁ ] generating the data for the first mode, and the upper significant data [01] are generated in two columns of encoder lines [LN₂₇₂ ] generating the data for the second mode, respectively, which are output to the selection gate 335.

Also, if the sampling voltage V_(S) is represented as V₃₅₂ <V_(S) <V₃₅₁ (=V₃₃₆), the output of the comparator CU₁₇₁ of the upper data comparator 331 becomes "L", and the output of the comparator CU₁₇₂ of the upper data comparator 332 becomes "H", so that the digital signals are output, i.e., "0" is output from the AND gates AU₁₇₁ and AU₁₇₃ of the upper data comparator 331, and "1" is output from the AND gate AU₁₇₂ of the upper data comparator 332, respectively.

As a result, a digital signal such as [010] is input to the upper data encoder 333 via the buffers BU₁₇₁ to BU₁₇₃. At the upper data encoder 333, using a so-called wired-OR circuit, the upper significant data are generated, i.e., [10] is generated in two columns of encoder lines [LN₂₇₁ ] generating the data for the first mode, and [01] is generated in two columns of encoder lines [LN₂₇₂ ] generating the data for the second mode, respectively, which are output to the selection gate 335.

Also, if the sampling voltage V_(S) is represented as V₃₅₁ <V_(S) <V_(RT), the output of the comparator CU₁₇₁ of the upper data comparator 331 becomes "H", and the output of the comparator CU₁₇₂ of the upper data comparator 332 becomes "L", so that the digital signals are output, i.e., "1" is output from the AND gate AU₁₇₁ of the upper data comparator 331, and "0" is output from the AND gates AU₁₇₂ and AU₁₇₃ of the upper data comparator 332, respectively.

As a result, a digital signal such as [100] is input to the upper data encoder 333 via the buffers BU₁₇₁ to BU₁₇₃. At the upper data encoder 333, using a so-called wired-OR circuit, the upper significant data are generated, i.e. [10] is generated in two columns of encoder lines [LN₂₇₁ ] generating the data for the first mode, and [11] is generated in two columns of encoder lines [LN₂₇₂ ] generating the data for the second mode, respectively, which are output to the selection gate 335.

In parallel with this, the transistors Q₂₆₃ of the respective switching blocks of the matrix circuit 330 connected to the control lines (x₁₇₁, x₁₇₂, x₁₇₃, x₁₇₄) at which the digital output signal has become "1" among the respective AND gates AU.sub.(171, 172, 173) are controlled to turn ON in units of rows and further a fine digitization of the quantization level is executed.

For example, when only the output of the AND gate AU₁₇₃ becomes the "1" level, the respective transistors Q₂₆₃ of the switching blocks S_(m41), S_(m43), S_(m45) and S_(m47) at the first row from the bottom in the diagram constituting the first group and the switching blocks S_(m32), S_(m34), S_(m36) and S_(m38) at the second row constituting the second group adjoining to them become ON, the reference voltages V₃₃₉ to V₃₄₅ divided by the reference resistances R₃₀₉ to R₃₁₆ and the sampling voltage V_(S) are differentially amplified at the respective switching blocks S_(m41), S_(m43), S_(m45) and S_(m47), and S_(m32), S_(m34), S_(m36) and S_(m38), and they are compared by the lower data comparators 341 to 348.

Similarly, when the output of the AND gate AU₁₇₂ is the "1" level, the switching blocks S_(m32), S_(m34), S_(m36) and S_(m38) at the second row and the switching blocks S_(m21), S_(m23), S_(m25) and S_(m27) at the third row adjoining to them are activated, so that the differential amplification operation is performed, and the comparison by the lower data comparators 341 to 348 is carried out.

For example, when the output of the AND gate AU₁₇₂ is the "1" level, the lower data conversion code is detected by the switching blocks S_(m21), S_(m23), S_(m32) and S_(m34), and the redundant bit of the lower significant data conversion code is detected by the switching blocks S_(m25), S_(m27), S_(m36) and S_(m38).

In this way, in the lower data conversion codes, the sampled voltage V_(S) and the reference voltage divided by the reference resistance elements are compared by the activated switching blocks, so that the digital signal in accordance with the result of comparison will be output from the AND gates AD₁₈₁ to AD₁₈₇ and AD₁₈₈ of the lower data comparators 341 to 348.

At this time, where the signal of the "1" level is output from one AND gate among the AND gates AD₁₈₁, AD₁₈₃, AD₁₈₅ and AD₁₈₇ of the lower data comparators 341, 343, 345 and 347 constituting the first group to the lower data encoder 334, at the lower data encoder 334, the selection line LN₂₇₄ becomes "1".

As a result, the selection signal SEL₁₇₁ is input to the selection gate 335 as the "1" level, and the selection signal SEL₁₇₂ is input to the selection gate 335 as the "0" level.

In the selection gate 335, along with the fact that only the selection signal SEL₁₇₁ is input as the "1" level, only the AND gates A₁₈₁ and A₁₈₃ are activated.

To these AND gates A₁₈₁ and A₁₈₃, the bit data on the upper data side and lower data side of the upper significant data for the first mode generated in the line LN₂₇₁ of the upper data encoder 333 are respectively supplied.

Accordingly, in the selection gate 335, the respective bits of the upper significant data at the time of the first mode are selected, and as a result, they are output as the upper significant data conversion codes D₁ and D₂ via the OR gates OR₃₀₁ and OR₃₀₂.

Concretely, when the sampling voltage V_(S) of the analog signal V_(IN) is defined as V_(RB) <V_(S) <V₃₅₂, the upper data conversion codes [D₁, D₂ ] are output as [00]; when V₃₅₂ <V_(S) <V₃₅₁ stands, the upper significant data conversion codes [D₁, D₂ ] are output as [10]; and when V₃₅₁ <V_(S) <V_(RT) stands, the upper significant data conversion codes [D₁, D₂ ] are output as [10].

Also, in the lower data encoder 334, when the output of the AND gate AD₁₈₁ of the lower data comparator 341 is "1", the lower data conversion codes D₃ and D₄ are generated as [00]; when the output of the AND gate AD₁₈₃ of the lower data comparator 343 is "1", the lower data conversion codes D₃ and D₄ are generated as [01]; when the output of the AND gate AD₁₈₅ of the lower data comparator 345 is "1", the lower data conversion codes D₃ and D₄ are generated as [10]; and when the output of the AND gate AD₁₈₇ of the lower data comparator 347 is "1", the lower data conversion codes D₃ and D₄ are generated as [11], which are output.

Where the signal of the "1" level is output from one AND gate among the AND gates AD₁₈₂, AD₁₈₄, AD₁₈₆ and AD₁₈₈ of the lower data comparators 342, 344, 346 and 348 constituting the second group to the lower data encoder 334, at the lower data encoder 334, the selection line LN₂₇₅ becomes "1".

As a result, the selection signal SEL₁₇₂ is input to the selection gate 335 as the "1" level, and the selection signal SEL₁₇₁ is input to the selection gate 335 as the "0" level.

In the selection gate 335, along with the fact that only the selection signal SEL₁₇₁ is input as the "1" level, only the AND gates A₁₈₂ and A₁₈₄ are activated.

To these AND gates A₁₈₂ and A₁₈₄, the bit data on the upper data side and lower data side of the upper significant data for the second mode generated in the line LN₂₇₂ of the upper data encoder 333 are respectively supplied.

Accordingly, in the selection gate 335, the respective bits of the upper significant data at the time of the second mode are selected, and as a result, they are output as the upper significant data conversion codes D₁ and D₂ via the OR gates OR₃₀₁ and OR₃₀₂.

Concretely, when the sampling voltage V_(S) of the analog signal V_(IN) is defined as V_(RB) <V_(S) <V₃₅₂, the upper data conversion codes [D₁, D₂ ] are output as [01]; when V₃₅₂ <V_(S) <V₃₅₁ stands, the upper significant data conversion codes [D₁, D₂ ] are output as [01]; and when V₃₅₁ <V_(S) <V_(RT) stands, the upper significant data conversion codes [D₁, D₂ ] are output as [11].

Also, in the lower data encoder 334, when the output of the AND gate AD₁₈₂ of the lower data comparator 342 is "1", the lower data conversion codes D₃ and D₄ are generated as [11]; when the output of the AND gate AD₁₈₄ of the lower data comparator 344 is "1", the lower data conversion codes D₃ and D₄ are generated as [10]; when the output of the AND gate A_(D6) of the lower data comparator 346 is "1", the lower data conversion codes D₃ and D₄ are generated as [01]; and when the output of the AND gate AD₁₈₈ of the lower data comparator 348 is "1", the lower data conversion codes D₃ and D₄ are generated as [00], which are output.

As explained above, according to the present embodiment, the reference voltages V₃₃₆ (=V₃₅₁) and V₃₄₀ (=V₃₅₂) supplied to the switching block positioned intermediate in the row direction between the second row and third row among the switching blocks arranged in the form of a matrix comprising 4 rows and 8 columns are supplied to the upper data comparators 331 and 332, respectively, the lower significant codes are divided to two groups, signals SEL₁₇₁ and SEL₁₇₂ for selecting the first mode data and second mode data are output from the lower data encoder 334 obtaining this group of conversion code, so that the first mode data and second mode data output from the upper data encoder 333 are selected, thereby obtaining the upper data conversion codes D₁ and D₂, and therefore it is possible to use the selection signal directly for the selection of the upper significant data without the use of the inverted gate and inhibit gate as in the conventional circuit.

Accordingly, the input of the selection signal to the selection gate 335 is not delayed relative to the output of the upper data encoder 333, and thus the increase of speed of conversion processing can be achieved.

Also, in addition to the fact that the inverted gate and inhibit gate become unnecessary, an increase of the number of the reference resistance columns can be prevented and, at the same time, the number of selection signals can be reduced to two. Also, the number of the upper significant code to be selected and the number of the input gate of the selection gate can be reduced to two, and further a reduction of the number of the switching blocks can be achieved.

Accordingly, there is an advantage that an A/D converter circuit with which the reduction of the surface area of the chip and the reduction of power consumption can be achieved can be realized.

FIG. 37 is a circuit diagram showing a 14th embodiment of the A/D converter circuit according to the present invention.

The point of difference of the 14th embodiment from the above-mentioned 13th embodiment resides in the constitution wherein, in the upper data encoder 363, in both of the first mode and second mode, the lower data side bit (minimum bit) D₂ of the upper data code is not generated, only the upper data side bit D₁ is generated, and the lower data side bit (minimum bit) D₂ is output as the upper significant data conversion code D₂ using the selection signal SEL₁₉₂ generated in the lower data encoder 364 as it is.

As seen from FIG. 36, as the upper least significant bit (the second bit from the highest bit of the 4-bit data in FIG. 36), "0" and "1" are alternately repeated for every row. This is similar to the selection signal SEL₁₉₂ corresponding to the second group.

Accordingly, even if the constitution is made so that the selection signal SEL₁₉₂ generated in the lower data encoder 364 is used as it is and output as the upper data conversion code D₂, it has the same function as that in the case of the above-mentioned 13th embodiment. Not only can similar effects be obtained, but also the reduction of the number of the upper data codes to be selected and the reduction of the OR-gates in the selection gate 366 can be achieved. Thus, there is an advantage that the reduction of the chip area and the reduction of the power consumption can be achieved.

FIG. 38 is a circuit diagram showing a 15th embodiment of the A/D converter circuit according to the present invention.

The point of difference of the 15th embodiment from the above-mentioned 15th embodiment resides in the constitution whereby the number of the selection lines of the lower data encoder 394 is reduced to only one line, i.e., LN₃₂₃, to generate only one selection signal SEL₂₀₁ as the selection signal, and a signal obtained by inverting the level of the selection signal SEL₂₀₁ at the inverter 397 is supplied as the signal in place of the selection signal SEL₁₉₁ to one input of the AND gate A₂₀₁ of the selection gate 395.

Namely, in the present 15th embodiment, the upper least significant data is produced at the lower data encoder 394, and that data is added to the selection terminal of a demultiplexer comprising the inverter 397 and the selection gate 395, whereby the selection of the upper significant data is carried out. In appearance, the selection signal is omitted.

According to the present 15th embodiment, similar effects to those obtained in the above-described 14th embodiment can be obtained.

Note that, in the above-mentioned 13th, 14th and 15th embodiments, an explanation was made taking as an example an A/D converter circuit for four bits, but needless to say the present invention can be applied to an A/D converter circuit for more bits as well.

Also, in the above-mentioned 13th, 14th and 15th embodiments, the structure in which the other output pin buffers are arranged on the input side of the upper data encoder and the lower data encoder was indicated, but these other output pin buffers are provided so as to reliably drive the upper data encoder and the lower data encoder, and it is necessary to provide the same according to a certain capacitance of the upper data encoder and the lower data encoder acting as a load.

As explained above, according to the present invention, the inverted gate and inhibit gate which have been conventionally necessary become unnecessary, and the increase of speed of conversion processing can be achieved.

Also, in addition to the fact that the inverted gate and inhibit gate become unnecessary, the increase of number of the resistance element columns can be prevented. At the same time, the number of the selection signals can be reduced, the number of the upper data codes to be selected and the number of the input gates of selection gates can be reduced, and further the number of the switching blocks can be reduced to the minimum level, and thus there is an advantage that the reduction of the chip area and the reduction of the power consumption can be achieved. 

What is claimed is:
 1. An analog/digital converter circuit comprising:a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by an upper data conversion output signal in units of rows, comparing the respective reference voltages divided by said reference resistance elements with an input signal to be converted, and detecting the presence/absence of lower significant bit data and redundant bit data, thereby providing a differential output; an upper data encoder comparing said reference voltage supplied to a switching block of said switching block matrix with said input signal to be converted, and providing a plurality of conversion codes of the upper significant bits in accordance with the result of said comparison: a lower data comparator circuit including first and second comparators with weights of outputs set to N and which provide a complementary output; a third comparator with a weight of output set to n₁ and which provides a complementary output; a fourth comparator with a weight of output set to n₂ (note, n₁ +n₂ =N) and which provides a complementary output; a first adder which adds one output of said third comparator and one output of said fourth comparator; and a second adder which adds the other output of said third comparator and the other output of said fourth comparator, wherein a differential output of one row of the switching block being connected to the inputs of said first comparator and said third comparator, and the differential output of the other row of said switching block being connected to the inputs of said second comparator and said fourth comparator; a lower data encoder, providing a predetermined lower data conversion code for the complementary outputs of the respective comparators of said lower data comparator in accordance with the presence/absence of the lower significant bit data and redundant bit data, and generating a selection signal for selecting one conversion code from among the conversion codes of the upper significant bits of said upper data encoder; and a selection gate selectively outputting one conversion code from among a plurality of conversion codes of the upper significant bits output from said upper data encoder based on the selection signal output from said lower data encoder.
 2. An analog/digital converter circuit according to claim 1, wherein said lower data comparator circuit includes a ring comparator comprising a plurality of comparator circuit, each including a first comparator or second comparator and a third comparator and fourth comparator corresponding to respective row of said switching blocks, inputs of the respective comparators being connected to the differential outputs of said switching blocks of the corresponding row and the outputs of said third and fourth comparators of each comparator circuit being connected to the output of said third comparator or fourth comparator of the other comparator circuit, andwherein said lower data comparator circuit includes a suppression circuit which cuts a predetermined position of said ring comparator in accordance with the upper data conversion output signal, and suppresses the unnecessary input of the output of the comparator to the lower data comparator.
 3. An analog/digital converter circuit according to claim 1, wherein the weights of outputs of said third and fourth comparators are set as n₁ =n₂ =N/2.
 4. An analog/digital converter circuit comprising:a plurality of switching blocks, arranged in the form of a matrix, comparing respective reference voltages provided by dividing a reference potential by a serially connected a plurality of resistance elements with an input signal to be converted; an upper data comparator comparing said reference voltage applied to the specific position of switching block in the row direction with an input signal to be converted, thereby providing the conversion code of the upper significant bit; a determining circuit determining whether the number of said switching blocks obtaining a comparison result that the level of said input signal to be converted is larger than the reference voltage level is even or odd; and a lower data encoder providing the conversion code of a lower significant bit in accordance with the result of determination of said determining circuit.
 5. An analog/digital converter circuit according to 4, wherein said plurality of switching blocks are simultaneously driven.
 6. An analog/digital converter circuit according to claim 4, wherein said respective switching blocks are constituted by differential type amplifiers, each having a pair of transistors the base of which being supplied with said input signal to be converted and said divided reference voltage; andwherein said determining circuit is constituted in that the transistor output to which said input signal is supplied and the transistor output to which said reference voltage is supplied are alternately connected for each row and are connected to a load element.
 7. An analog/digital converter circuit according to claim 4, wherein said determining circuit includes a means which performs the exclusive-OR of the adjoining switching blocks for each row and outputs the total sum thereof to said lower data encoder.
 8. An analog/digital converter circuit according to claim 7, wherein said determining circuit has a plurality of exclusive-OR gates performing the exclusive-OR of the outputs of the adjoining switching blocks and constituted so that the outputs of said respective exclusive-OR gates are connected.
 9. An analog/digital converter circuit according to claim 4, wherein said plurality of resistance elements are arranged in a plurality of rows by folding-back so that the direction of application of said reference voltage becomes reverse for each predetermined number of reference resistance elements, andwherein provision is made of an inverted gate which inverts, when a direction of application of voltage of a predetermined row is used as a reference, said obtained significant data conversion code obtained based on said reference voltage by said reference resistance elements of the row in the direction of application which is reverse to the former and outputs the same.
 10. An analog/digital converter circuit comprising:a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by an upper data conversion output signal for each row, comparing respective reference voltages divided by said reference resistance elements with an input signal to be converted, and detecting the presence/absence of the lower significant bit data and redundant bit data for each predetermined row; an upper data encoder, comparing said reference voltage at a specific portion in the row direction of said switching block with said input signal to be converted, and providing the conversion code of said upper significant bit in accordance with a redundant mode or non-redundant mode which are set in advance; a lower data encoder, providing the conversion code of the lower significant bit and the conversion code of the redundant bit out of the conversion range specified by said upper encoder from the outputs of said respective switching blocks in accordance with the presence/absence of the lower significant bit data and the redundant bit data, and generating a selection signal in accordance with the redundant mode or non-redundant mode in accordance with the presence/absence of the redundant bit data; and a selection gate selectively outputting the conversion code of the upper significant bit in accordance with said redundant mode or non-redundant mode from among the conversion codes of the upper significant bit in accordance with said redundant mode or said non-redundant mode output from said upper data encoder based on said selection signal in accordance with the mode output from said lower data encoder.
 11. An analog/digital converter circuit according to claim 10, wherein said reference resistance elements are arranged by folding-back so as to extend over a predetermined number of rows so as to correspond to the matrix arrangement of said switching blocks; andwherein the output conversion code value of said redundant mode or non-redundant mode in said upper data encoder is set in accordance with the transition direction of the reference voltage level for each row.
 12. An analog/digital converter circuit according to claim 10, wherein said switching block rows detecting the redundant bit data, among the switching blocks arranged in the form of a matrix, are positioned on both sides of the switching block row detecting the lower significant bit data, and one switching block column and the other switching block column detect different redundant mode data;wherein said upper data encoder outputs the conversion code of the upper significant bit in accordance with said redundant mode or said non-redundant mode; and wherein the output conversion code values of said upper data encoder are set so as to have a difference of magnitude in an order of one redundant mode, and said non-redundant mode, and the other redundant mode.
 13. An analog/digital converter circuit comprising:a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by an upper data conversion output signal for each row, comparing the respective reference voltages divided by said reference resistance elements with an input signal to be converted, and detecting the presence/absence of lower significant bit data and redundant bit data; at least one data change point detection circuit comparing the reference voltage generated between mutually adjoining rows excluding at least the uppermost row or lowermost row of switching block matrix with said input signal to be converted, and detecting the change point of data; an upper data encoder providing the conversion code of the upper significant bit in accordance with 2 modes set in advance in accordance with the result of detection of said data change point detection circuit; a lower data encoder dividing the outputs of said respective switching blocks in units of rows into two groups in accordance with said 2 modes, providing the predetermined lower data conversion code in accordance with the presence/absence of the lower significant bit data and redundant bit data for each of the respective divided groups, and generating a selection signal for selecting one selection code from among the two upper significant bits of conversion codes of said upper data encoder; and a selection gate selectively outputting one conversion code selected from among two upper significant bits of conversion codes output from said upper data encoder based on the selection signal output from said lower data encoder.
 14. An analog/digital converter circuit according to claim 13, wherein said reference resistance elements are arranged by folding-back so as to extend over a predetermined number of rows so as to correspond to the matrix arrangement of said switching blocks, and the row of the resistance elements generating the reference voltage of the highest value and the row of the resistance elements generating the reference voltage of the lowest value are arranged with a deviation of a predetermined cycle relative to the row of the other resistance elements; andwherein the output conversion code value of said upper data encoder is set in accordance with the transition direction of the reference voltage level for each row.
 15. An analog/digital converter circuit according to claim 14, wherein said predetermined cycle is a half cycle.
 16. An analog/digital converter circuit according to claim 13, wherein the constitution is made so that the switching block columns arranged in the form of a matrix are divided into two column groups with a predetermined column as the reference and outputs of these column groups correspond to two groups of said lower data encoder; andwherein the values of the output conversion codes of said upper data encoder have a difference of magnitude in an order of one mode and the other mode.
 17. An analog/digital converter circuit according to claim 13, wherein said two groups are divided with the switching point of the upper significant bit in the output conversion code as the reference.
 18. An analog/digital converter circuit according to claim 13, wherein the above-described lower data encoder is constituted so as to generate two selection signals in accordance with two divided groups.
 19. An analog/digital converter circuit according to claim 13, wherein said lower data encoder is constituted so as to generate one selection signal in accordance with one group among two divided groups.
 20. An analog/digital converter circuit comprising:a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by an upper data conversion output signal for each row, comparing the respective reference voltages divided by said reference resistance elements with an input signal to be converted, and detecting the presence/absence of lower significant bit data and redundant bit data; an upper data encoder, comparing said reference voltage applied to the specific position of said switching block in the row direction with said input signal to be converted, and providing the two conversion codes of the upper significant bit excluding the predetermined bits among the upper significant bits in accordance with 2 modes set in advance; a lower data encoder, dividing the outputs of said respective switching blocks in units of columns into two groups in accordance with said 2 modes, providing the predetermined lower data conversion code in accordance with the lower significant bit data and the presence/absence of the redundant bit data for each of divided groups, and generating the selection signal for selecting one conversion code from among 2 upper significant bits of conversion codes of said upper data encoder; and a selection gate selectively outputting one conversion code selected from among 2 upper significant bits of conversion codes output from said upper data encoder based on the selection signal output from said lower data encoder, said selection signal being output as the predetermined bit of the upper significant conversion code excluded at the upper data encoder.
 21. An analog/digital converter circuit according to claim 20, wherein the bit excluded at said upper data encoder is the least significant bit of the upper significant bits; andwherein said selection signal is output as the conversion code of the least significant bit in the upper significant bits.
 22. An analog/digital converter circuit according to claim 20, wherein said reference resistance elements are arranged by folding-back so as to extend over a predetermined number of rows so as to correspond to the matrix arrangement of said switching blocks, and the row of the resistance elements generating the reference voltage of the highest value and the row of said resistance elements generating the reference voltage of the lowest value are arranged with a deviation of a predetermined cycle relative to the row of the other resistance elements.
 23. An analog/digital converter circuit according to claim 20, wherein said predetermined cycle is a half cycle.
 24. An analog/digital converter circuit according to claim 20, wherein the constitution is made so that the switching block columns arranged in the form of a matrix are divided into two column groups with a predetermined column as the reference, and outputs of these column groups correspond to two groups of said lower data encoder.
 25. An analog/digital converter circuit according to claim 20, wherein said two groups are divided with the switching point of the upper significant bit in the output conversion code as the reference.
 26. An analog/digital converter circuit according to claim 20, wherein said lower data encoder is constituted so as to generate two selection signals in accordance with two divided groups, andwherein one selection signal selected from among two selection signals is output as the upper data conversion code of a predetermined bit excluded at the upper data encoder.
 27. An analog/digital converter circuit according to claim 20, wherein said upper data encoder is constituted so as to generate one selection signal in accordance with one block among two divided groups; andwherein said analog/digital converter circuit includes a means which inverts the level of the generated selection signal and outputs the same as the upper data conversion code of the predetermined bit excluded at the upper data encoder.
 28. An analog/digital converter circuit comprising:a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by the upper data conversion output signal for each sow, comparing the respective reference voltages divided by said reference resistance elements with an input signal to be converted, and detecting the presence/absence of lower significant bit data and redundant bit data; an upper data encoder, comparing the reference voltage applied to the specific position of switching block in the row direction with said input signal to be converted, and providing the conversion code of the upper significant bit in accordance with 2 modes set in advance; a lower data encoder dividing the outputs of said respective switching blocks in units of columns into two groups in accordance with said 2 modes, providing the predetermined lower data conversion code in accordance with the lower significant bit data and the presence/absence of the redundant bit data for each of divided groups, and generating the selection signal for selecting one conversion code from among 2 upper significant bits of conversion codes of said upper data encoder; and a selection gate selectively outputting one conversion code selected from among 2 upper significant bits of conversion codes output from said upper data encoder based on the selection signal output from said lower data encoder.
 29. An analog/digital converter circuit according to claim 28, wherein said reference resistance elements are arranged by folding-back so as to extend over a predetermined number of rows so as to correspond to the matrix arrangement of said switching blocks, and the row of the resistance elements generating the reference voltage of the highest value and the row of the resistance elements generating the reference voltage of the lowest value are arranged with a deviation of a predetermined cycle relative to the row of the other resistance elements; andwherein the output conversion code value of said upper data encoder is set in accordance with the transition direction of the reference voltage level for each row.
 30. An analog/digital converter circuit according to claim 29, wherein said predetermined cycle is a half cycle.
 31. An analog/digital converter circuit according to claim 28, wherein the constitution is made so that the switching block rows arranged in the form of a matrix are divided into two row groups with a predetermined column as the reference, and outputs of these column groups correspond to two groups of said lower data encoder; andwherein the output conversion code value of said upper data encoder is set so as to have a difference of magnitude in an order of one mode and the other mode.
 32. An analog/digital converter circuit according to claim 28, wherein said two groups are divided with the switching point of the upper significant bit in the output conversion code as a reference.
 33. An analog/digital converter circuit according to claim 28, wherein said lower data encoder is constituted so as to generate two selection signals in accordance with two divided groups.
 34. An analog/digital converter circuit according to claim 28, wherein said upper data encoder is constituted so as to generate one selection signal in accordance with one block among two divided groups.
 35. An analog/digital converter circuit comprising:a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by the upper data conversion output signal for each row, comparing the respective reference voltages divided by said reference resistance elements with an input signal to be converted, and detecting the presence/absence of lower significant bit data and redundant bit data; an upper data encoder comparing the reference voltage supplied to the switching block positioned intermediate in the rows excluding at least the uppermost row or lowermost row with said input signal to be converted, and providing the conversion code of the upper significant bit in accordance with 2 modes set in advance; lower data encoder dividing the outputs of said respective switching blocks in units of columns into two groups in accordance with said 2 modes, providing the predetermined lower data conversion code in accordance with the lower significant bit data and the presence/absence of the redundant bit data for each of divided groups, and generating the selection signal for selecting one conversion code from among 2 upper significant bits of conversion codes of said upper data encoder; and a selection gate selectively outputting one conversion code selected from among 2 upper significant bits of conversion codes output from said upper data encoder based on the selection signal output from said lower data encoder.
 36. An analog/digital converter circuit according to claim 35, wherein said reference resistance elements are arranged by folding-back so as to extend over a predetermined number of rows so as to correspond to the matrix arrangement of said switching blocks;wherein it is constituted so that the switching block columns arranged in the form of a matrix are divided into two groups of the odd number columns and even number columns, and the outputs of these column groups correspond to two groups of said lower data encoder; and wherein said lower data encoder is constituted by a ring comparator which has a plurality of outputs, receives the outputs of the switching block columns, and makes only predetermined one output active and a lower significant code line and a selection line wired-connected so as to output the respective outputs of said ring comparator and the binary signal in accordance with the divided groups and said ring comparator.
 37. An analog/digital converter circuit according to claim 35, wherein said lower data encoder is constituted so as to generate two selection signals in accordance with two divided groups.
 38. An analog/digital converter circuit according to claim 35, wherein said lower data encoder is constituted so as to generate one selection signal in accordance with one group among the two divided groups.
 39. An analog/digital converter circuit according to claim 35, wherein said upper data encoder is constituted so as to obtain two conversion codes comprising upper significant bits excluding the least significant bit; andwherein the predetermined selection signal is output as the conversion code of the least significant bit in the upper significant bits. 